SNOSDG0 August   2024 TLV1H103-SEP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Diagrams
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
    4. 6.4 Device Functional Modes
      1. 6.4.1 Inputs
      2. 6.4.2 Push-Pull (Single-Ended) Output
      3. 6.4.3 Known Startup Condition
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Adjustable Hysteresis
      2. 7.1.2 Capacitive Loads
      3. 7.1.3 Latch Functionality
    2. 7.2 Typical Application
      1. 7.2.1 Implementing Adjustable Hystseresis
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curve
      2. 7.2.2 Optical Receiver
      3. 7.2.3 Over-Current Latch Condition
      4. 7.2.4 External Trigger Function
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Documentation Support
    1. 8.1 Related Documentation
      1. 8.1.1 Development Support
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3 Power Supply Recommendations

The TLV1H103-SEP is designed for operation from 2.4V to 5.5V. While most applications require single supply operation where VEE is connected to the ground and VCC is connected to the intended power supply level, the comparators can also be operated with split supplies. One caution when using split supplies is that the output logic levels are determined by the VCC and VEE levels. For example, if split supplies of +/- 2.5V are used, the output levels are 2.5V and -2.5V accordingly. In addition, the logic level of the LE/HYS pin is also referenced to VEE. This means that the external hysteresis resistor or voltage source on the TLV1H103-SEP needs to be connected between the LE/HYS pin and VEE (not to ground) for proper operation.

Regardless of single supply or split supply operation, proper decoupling capacitors are required. TI recommends using a scheme of multiple, low-ESR ceramic capacitors from the supply pins to the ground plane for optimum performance. A good combination is 100pF, 10nF, and 1uF with the lowest value capacitors closest to the comparator.