SNOSDG0 August   2024 TLV1H103-SEP

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Diagrams
    7. 5.7 Typical Characteristics
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
    4. 6.4 Device Functional Modes
      1. 6.4.1 Inputs
      2. 6.4.2 Push-Pull (Single-Ended) Output
      3. 6.4.3 Known Startup Condition
  8. Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Adjustable Hysteresis
      2. 7.1.2 Capacitive Loads
      3. 7.1.3 Latch Functionality
    2. 7.2 Typical Application
      1. 7.2.1 Implementing Adjustable Hystseresis
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curve
      2. 7.2.2 Optical Receiver
      3. 7.2.3 Over-Current Latch Condition
      4. 7.2.4 External Trigger Function
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. Documentation Support
    1. 8.1 Related Documentation
      1. 8.1.1 Development Support
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Over-Current Latch Condition

When the design is required to detect a brief over-current condition, the latching feature of the TLV1H103-SEP can be utilized. By latching the comparator output, the MCU does not miss the over-current occurrence. The circuit below shows one way to implement the latching function.

When an over-current condition is detected by the TLV1H103-SEP, the output transitions high. The occurrence of the output going high coupled with a logic high from the RESET signal from the MCU creates a logic low signal at the output of the 2-channel NAND gate. This causees the output of the TLV1H103-SEP to be held in a logic high state (latched), thus allowing the MCU to detect the fault condition regardless of how narrow the over-current condition persists. The addition of the NAND gate also provides a means of clearing the latch state of the comparator once the MCU is done processing the event. This is accomplished by the MCU passing a logic low state to the NAND input causing the LE/HYS pin of the comparator to be returned to a logic high state. The latched status is cleared and the TLV1H103-SEP output can continue to track the status of the input pins.

Over-Current Latched Output Circuit

TLV1H103-SEP