SNOSDG0 August   2024 TLV1H103-SEP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Diagrams
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
    4. 6.4 Device Functional Modes
      1. 6.4.1 Inputs
      2. 6.4.2 Push-Pull (Single-Ended) Output
      3. 6.4.3 Known Startup Condition
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Adjustable Hysteresis
      2. 7.1.2 Capacitive Loads
      3. 7.1.3 Latch Functionality
    2. 7.2 Typical Application
      1. 7.2.1 Implementing Adjustable Hystseresis
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curve
      2. 7.2.2 Optical Receiver
      3. 7.2.3 Over-Current Latch Condition
      4. 7.2.4 External Trigger Function
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Documentation Support
    1. 8.1 Related Documentation
      1. 8.1.1 Development Support
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.7 Typical Characteristics

At TA = 25°C, VCC - VEE = 2.5V to 5V, VCM = 300mV, RHYST = 150kΩ, and input overdrive = 50mV, unless otherwise noted.

TLV1H103-SEP Offset vs. TemperatureFigure 5-3 Offset vs. Temperature
TLV1H103-SEP Offset vs. Common-Mode, 2.5VFigure 5-5 Offset vs. Common-Mode, 2.5V
TLV1H103-SEP Offset vs. Common-Mode, 3.3VFigure 5-7 Offset vs. Common-Mode, 3.3V
TLV1H103-SEP Offset vs. Common-Mode, 5VFigure 5-9 Offset vs. Common-Mode, 5V
TLV1H103-SEP Hysteresis vs. Resistance, 2.5VFigure 5-11 Hysteresis vs. Resistance, 2.5V
TLV1H103-SEP Hysteresis vs. Resistance, 5VFigure 5-13 Hysteresis vs. Resistance, 5V
TLV1H103-SEP Bias Current vs. Input Voltage, 3.3VFigure 5-15 Bias Current vs. Input Voltage, 3.3V
TLV1H103-SEP Output Voltage vs. Output Sourcing Current, 2.5VFigure 5-17 Output Voltage vs. Output Sourcing Current, 2.5V
TLV1H103-SEP Output Voltage vs. Output Sourcing Current, 3.3VFigure 5-19 Output Voltage vs. Output Sourcing Current, 3.3V
TLV1H103-SEP Output Voltage vs. Output Sourcing Current, 5VFigure 5-21 Output Voltage vs. Output Sourcing Current, 5V
TLV1H103-SEP Supply Current vs. Voltage (Output Low)Figure 5-23 Supply Current vs. Voltage (Output Low)
TLV1H103-SEP Supply Current vs. Temp (Output Low)Figure 5-25 Supply Current vs. Temp (Output Low)
TLV1H103-SEP Propagation Delay, Low to High, 2.5VFigure 5-27 Propagation Delay, Low to High, 2.5V
TLV1H103-SEP Propagation Delay, Low to High, 3.3VFigure 5-29 Propagation Delay, Low to High, 3.3V
TLV1H103-SEP Propagation Delay, Low to High, 5VFigure 5-31 Propagation Delay, Low to High, 5V
TLV1H103-SEP Propagation Delay vs. Load Capacitance, 3.3VFigure 5-33 Propagation Delay vs. Load Capacitance, 3.3V
TLV1H103-SEP Minimum Pulse Width vs. TemperatureFigure 5-35 Minimum Pulse Width vs. Temperature
TLV1H103-SEP Hysteresis Voltage vs. LE/HYST Voltage, 3.3VFigure 5-37 Hysteresis Voltage vs. LE/HYST Voltage, 3.3V
TLV1H103-SEP Hysteresis vs. TemperatureFigure 5-4 Hysteresis vs. Temperature
TLV1H103-SEP Hysteresis vs. Common-Mode, 2.5VFigure 5-6 Hysteresis vs. Common-Mode, 2.5V
TLV1H103-SEP Hysteresis vs. Common-Mode, 3.3VFigure 5-8 Hysteresis vs. Common-Mode, 3.3V
TLV1H103-SEP Hysteresis vs. Common-Mode, 5VFigure 5-10 Hysteresis vs. Common-Mode, 5V
TLV1H103-SEP Hysteresis vs. Resistance, 3.3VFigure 5-12 Hysteresis vs. Resistance, 3.3V
TLV1H103-SEP Bias Current vs. Input Voltage, 2.5VFigure 5-14 Bias Current vs. Input Voltage, 2.5V
TLV1H103-SEP Bias Current vs. Input Voltage, 5VFigure 5-16 Bias Current vs. Input Voltage, 5V
TLV1H103-SEP Output Voltage vs. Output Sinking Current, 2.5VFigure 5-18 Output Voltage vs. Output Sinking Current, 2.5V
TLV1H103-SEP Output Voltage vs. Output Sinking Current, 3.3VFigure 5-20 Output Voltage vs. Output Sinking Current, 3.3V
TLV1H103-SEP Output Voltage vs. Output Sinking Current, 5VFigure 5-22 Output Voltage vs. Output Sinking Current, 5V
TLV1H103-SEP Supply Current vs. Voltage (Output High)Figure 5-24 Supply Current vs. Voltage (Output High)
TLV1H103-SEP Supply Current vs. Temp (Output High)Figure 5-26 Supply Current vs. Temp (Output High)
TLV1H103-SEP Propagation Delay, High to Low, 2.5VFigure 5-28 Propagation Delay, High to Low, 2.5V
TLV1H103-SEP Propagation Delay, High to Low, 3.3VFigure 5-30 Propagation Delay, High to Low, 3.3V
TLV1H103-SEP Propagation Delay, High to Low, 5VFigure 5-32 Propagation Delay, High to Low, 5V
TLV1H103-SEP Propagation Delay vs. Load Capacitance, 5VFigure 5-34 Propagation Delay vs. Load Capacitance, 5V
TLV1H103-SEP Hysteresis Voltage vs. LE/HYST Voltage, 2.5VFigure 5-36 Hysteresis Voltage vs. LE/HYST Voltage, 2.5V
TLV1H103-SEP Hysteresis Voltage vs. LE/HYST Voltage, 5VFigure 5-38 Hysteresis Voltage vs. LE/HYST Voltage, 5V