The TLVx172 family of electromagnetic interference (EMI)-hardened, 36-V, single-supply, low-noise operational amplifiers (op amps) features a THD+N of 0.0002% at 1 kHz with the ability to operate on supplies ranging from 4.5 V (±2.25 V) to 36 V (±18V). These features, along with low noise and very high PSRR, enable the TLVx172 to amplify microvolt-level signals in applications such as HEV and EV automobiles and power trains, medical instrumentation, and more. The TLVx172 device offers good offset and drift, a high bandwidth of 10 MHz, and a slew rate of 10 V/μs with only 2.3 mA of quiescent current over temperature (maximum).
Unlike most op amps that are specified at only one supply voltage, the TLVx172 device is specified from 4.5 V to 36 V. Input signals beyond the supply rails do not cause phase reversal. TLVx172 device is stable with capacitive loads up to 300 pF. The input can operate 100 mV below the negative rail and within 2 V of the positive rail for normal operation. Note that the device can operate with a full rail-to-rail input 100 mV beyond the positive rail, but with reduced performance within 2 V of the positive rail.
The TLVx172 op amp is specified from –40°C to +125°C.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TLV172 | SOIC (8) | 4.90 mm × 3.91 mm |
SC70 (5) | 2.00 mm × 1.25 mm | |
SOT-23 (5) | 2.90 mm × 1.60 mm | |
TLV2172 | SOIC (8) | 4.90 mm × 3.91 mm |
VSSOP (8) | 3.00 mm × 3.00 mm | |
TLV4172 | SOIC (14) | 8.65 mm × 3.91 mm |
TSSOP (14) | 5.00 mm × 4.40 mm |
Changes from B Revision (September 2018) to C Revision
Changes from A Revision (May 2018) to B Revision
Changes from * Revision (November 2016) to A Revision
PIN | I/O | DESCRIPTION | |||
---|---|---|---|---|---|
NAME | SC70 | SOT-23 | SOIC | ||
–IN | 3 | 4 | 2 | I | Negative (inverting) input |
+IN | 1 | 3 | 3 | I | Positive (noninverting) input |
NC | — | — | 1, 5, 8 | — | No internal connection (can be left floating) |
OUT | 4 | 1 | 6 | O | Output |
V– | 2 | 2 | 4 | — | Negative (lowest) power supply |
V+ | 5 | 5 | 7 | — | Positive (highest) power supply |
PIN | I/O | DESCRIPTION | ||
---|---|---|---|---|
NAME | SOIC
(D) |
VSSOP
(DGK) |
||
–IN A | 2 | 2 | I | Inverting input, channel A |
–IN B | 6 | 6 | I | Inverting input, channel B |
+IN A | 3 | 3 | I | Noninverting input, channel A |
+IN B | 5 | 5 | I | Noninverting input, channel B |
OUT A | 1 | 1 | O | Output, channel A |
OUT B | 7 | 7 | O | Output, channel B |
V– | 4 | 4 | — | Negative (lowest) power supply |
V+ | 8 | 8 | — | Positive (highest) power supply |
PIN | I/O | DESCRIPTION | ||
---|---|---|---|---|
NAME | SOIC
(D) |
TSSOP
(PW) |
||
–IN A | 2 | 2 | I | Inverting input, channel A |
–IN B | 6 | 6 | I | Inverting input, channel B |
–IN C | 9 | 9 | I | Inverting input, channel C |
–IN D | 13 | 13 | I | Inverting input, channel D |
+IN A | 3 | 3 | I | Noninverting input, channel A |
+IN B | 5 | 5 | I | Noninverting input, channel B |
+IN C | 10 | 10 | I | Noninverting input, channel C |
+IN D | 12 | 12 | I | Noninverting input, channel D |
OUT A | 1 | 1 | O | Output, channel A |
OUT B | 7 | 7 | O | Output, channel B |
OUT C | 8 | 8 | O | Output, channel C |
OUT D | 14 | 14 | O | Output, channel D |
V– | 11 | 11 | — | Negative (lowest) power supply |
V+ | 4 | 4 | — | Positive (highest) power supply |
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
Voltage | Supply voltage, [(V+) – (V−)] | 40 | V | ||
Single-supply voltage | 40 | ||||
Signal input pin(2) | Common-mode | (V–) – 0.5 | (V+) + 0.5 | ||
Differential(3) | –0.5 | 0.5 | |||
Current | Signal input pin | –10 | 10 | mA | |
Output short-circuit(4) | Continuous | ||||
Temperature | Operating, TA | –55 | 150 | °C | |
Junction, TJ | 150 | ||||
Storage, Tstg | –65 | 150 |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±4000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±1000 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
Supply voltage, (V+) – (V–) | Single-supply | 4.5 | 36 | V | |
Dual-supply | ±2.25 | ±18 | |||
Specified temperature | –40 | 125 | °C |
THERMAL METRIC(1) | TLV172 | UNIT | |||
---|---|---|---|---|---|
D (SOIC) | DBV (SOT-23) | DCK (SC70) | |||
8 PINS | 5 PINS | 5 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 126.5 | 227.9 | 285.2 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 80.6 | 115.7 | 60.5 | °C/W |
RθJB | Junction-to-board thermal resistance | 67.1 | 65.9 | 78.9 | °C/W |
ψJT | Junction-to-top characterization parameter | 31.0 | 10.7 | 0.8 | °C/W |
ψJB | Junction-to-board characterization parameter | 65.6 | 65.3 | 77.9 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | — | — | — | °C/W |
THERMAL METRIC(1) | TLV2172 | UNIT | ||
---|---|---|---|---|
D (SOIC) | DGK (VSSOP) | |||
8 PINS | 8 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 116.1 | 158 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 69.8 | 48.6 | °C/W |
RθJB | Junction-to-board thermal resistance | 56.6 | 78.7 | °C/W |
ψJT | Junction-to-top characterization parameter | 22.5 | 3.9 | °C/W |
ψJB | Junction-to-board characterization parameter | 56.1 | 77.3 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | — | — | °C/W |
THERMAL METRIC(1) | TLV4172 | UNIT | ||
---|---|---|---|---|
D (SOIC) | PW (TSSOP) | |||
14 PINS | 14 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 82.7 | 111.1 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 42.3 | 40.8 | °C/W |
RθJB | Junction-to-board thermal resistance | 37.3 | 54.1 | °C/W |
ψJT | Junction-to-top characterization parameter | 8.9 | 3.8 | °C/W |
ψJB | Junction-to-board characterization parameter | 37 | 53.3 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | — | — | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
OFFSET VOLTAGE | |||||||
VOS | Input offset voltage | TA = 25°C | 0.5 | 1.7 | mV | ||
TA = –40°C to +125°C | 2 | ||||||
dVOS/dT | Input offset voltage drift | TA = –40°C to +125°C | 1 | µV/°C | |||
PSRR | Power-supply rejection ratio | VS = 4 V to 36 V, TA = –40°C to +125°C | 100 | 120 | dB | ||
Channel separation, dc | 5 | µV/V | |||||
INPUT BIAS CURRENT | |||||||
IB | Input bias current | TA = 25°C | ±10 | pA | |||
IOS | Input offset current | TA = 25°C | ±2 | pA | |||
NOISE | |||||||
Input voltage noise | f = 0.1 Hz to 10 Hz | 2.5 | µVPP | ||||
en | Input voltage noise density | f = 100 Hz | 14 | nV/√Hz | |||
f = 1 kHz | 9 | nV/√Hz | |||||
in | Input current noise density | f = 1 kHz | 1.6 | fA/√Hz | |||
INPUT VOLTAGE | |||||||
VCM | Common-mode voltage range(1) | (V–) – 0.1 | (V+) – 2 | V | |||
CMRR | Common-mode rejection ratio | VS = ±18 V, (V–) – 0.1 V < VCM < (V+) – 2 V,
TA = –40°C to +125°C |
94 | 116 | dB | ||
INPUT IMPEDANCE | |||||||
Differential | 100 || 4 | MΩ || pF | |||||
Common-mode | 6 || 4 | 1013 Ω || pF | |||||
OPEN-LOOP GAIN | |||||||
AOL | Open-loop voltage gain | (V–) + 0.35 V < VO < (V+) – 0.35 V, TA = –40°C to +125°C | 97 | 115 | dB | ||
(V–) + 0.5 V < VO < (V+) – 0.5 V,
RL = 2 kΩ, TA = –40°C to +125°C |
107 | ||||||
FREQUENCY RESPONSE | |||||||
GBP | Gain bandwidth product | 10 | MHz | ||||
SR | Slew rate | G = +1 | 10 | V/µs | |||
tS | Settling time | To 0.1%, VS = ±18 V, G = +1, 10-V step | 2 | µs | |||
To 0.01% (12-bit), VS = ±18 V, G = +1, 10-V step | 3.2 | ||||||
Overload recovery time | VIN × gain > VS | 200 | ns | ||||
THD+N | Total harmonic distortion + noise | VS = 36 V, G = +1, f = 1 kHz, VO = 3.5 VRMS | 0.0002% | ||||
OUTPUT | |||||||
VO | Voltage output swing from rail | VS = ±18 V, RL = 10 kΩ | TA = 25°C | 70 | mV | ||
TA = –40°C to +125°C | 95 | ||||||
VS = ±18 V, RL = 2 kΩ | TA = 25°C | 330 | 400 | ||||
TA = –40°C to +125°C | 470 | 530 | |||||
ISC | Short-circuit current | ±75 | mA | ||||
CLOAD | Capacitive load drive | See Typical Characteristics | pF | ||||
RO | Open-loop output resistance | f = 1 MHz, IO = 0 A | 60 | Ω | |||
POWER SUPPLY | |||||||
VS | Specified voltage range | 4.5 | 36 | V | |||
IQ | Quiescent current per amplifier | IO = 0 A, TA = –40°C to +125°C | 1.6 | 2.3 | mA |
DESCRIPTION | FIGURE |
---|---|
Offset Voltage Production Distribution | Figure 1 |
Offset Voltage vs Common-Mode Voltage | Figure 2 |
Offset Voltage vs Common-Mode Voltage (Upper Stage) | Figure 3 |
Input Bias Current vs Temperature | Figure 4 |
Output Voltage Swing vs Output Current (Maximum Supply) | Figure 5 |
CMRR and PSRR vs Frequency (Referred-to-Input) | Figure 6 |
0.1-Hz to 10-Hz Noise | Figure 7 |
Input Voltage Noise Spectral Density vs Frequency | Figure 8 |
Quiescent Current vs Supply Voltage | Figure 9 |
Open-Loop Gain and Phase vs Frequency | Figure 10 |
Closed-Loop Gain vs Frequency | Figure 11 |
Open-Loop Output Impedance vs Frequency | Figure 12 |
Small-Signal Overshoot vs Capacitive Load | Figure 13, Figure 14 |
No Phase Reversal | Figure 15 |
Small-Signal Step Response (10 mV) | Figure 16, Figure 17 |
Large-Signal Step Response | Figure 18, Figure 19 |
Large-Signal Settling Time | Figure 20, Figure 21 |
Short-Circuit Current vs Temperature | Figure 22 |
Maximum Output Voltage vs Frequency | Figure 23 |
EMIRR IN+ vs Frequency | Figure 24 |
Distribution taken from 5185 amplifiers |
5 typical units shown, VS = ±18 V |
100-mV output step, G = –1 | ||
RL = 1 kΩ | CL = 10 pF | 10-mV step |
RL = 1 kΩ | CL = 10 pF |
10-V negative step | G = 1 | CL = 10 pF |
5 typical units shown, VS = ±18 V |
CLOAD = 15 pF |
100-mV output step, G = 1 | ||
CL = 10 pF | 10-mV step |
CL = 10 pF |
10-V positive step | G = 1 | CL = 10 pF |
PRF = –10 dBm | VSUPPLY = ±18 V | VCM = 0 V |
The TLVx172 operational amplifier provides high overall performance, making these devices designed for many general-purpose applications. The excellent offset drift of only 1 μV/°C provides excellent stability over the entire temperature range. In addition, the device offers very good overall performance with high CMRR, PSRR, and AOL.
The TLVx172 amplifier is specified for operation from 4.5 V to 36 V (±2.25 V to ±18 V). Many of the specifications apply from –40°C to +125°C. Parameters that can exhibit significant variance with regard to operating voltage or temperature are shown in the Typical Characteristics section.
The TLVx172 device has an internal phase-reversal protection. Many operational amplifiers exhibit a phase reversal when the input is driven beyond the linear common-mode range. This condition is most often encountered in noninverting circuits when the input is driven beyond the specified common-mode voltage range, causing the output to reverse into the opposite rail. The input of the TLVx172 prevents phase reversal with excessive common-mode voltage. Instead, the output limits into the appropriate rail. This performance is shown in Figure 25.
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress. These questions tend to focus on the device inputs, but can involve the supply voltage pins or even the output pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin. Additionally, internal electrostatic discharge (ESD) protection is built into these circuits for protection from accidental ESD events both before and during product assembly.
A good understanding of this basic ESD circuitry and the relevance to an electrical overstress event is helpful. Figure 26 shows the ESD circuits contained in the TLVx172 (indicated by the dashed box). The ESD protection circuitry involves several current-steering diodes connected from the input and output pins and routed back to the internal power-supply lines, where the diodes meet at an absorption device internal to the operational amplifier. This protection circuitry is intended to remain inactive during normal circuit operation.
An ESD event produces a short-duration, high-voltage pulse that is transformed into a short-duration, high-current pulse when discharging through a semiconductor device. The ESD protection circuits are designed to provide a current path around the operational amplifier core to prevent damage. The energy absorbed by the protection circuitry is then dissipated as heat.
When an ESD voltage develops across two or more amplifier device pins, current flows through one or more steering diodes. Depending on the path that the current takes, the absorption device can activate. The absorption device has a trigger, or threshold voltage, that is above the normal operating voltage of the TLVx172 but below the device breakdown voltage level. When this threshold is exceeded, the absorption device quickly activates and clamps the voltage across the supply rails to a safe level.
When the operational amplifier connects into a circuit, as shown in Figure 26, the ESD protection components are intended to remain inactive and do not become involved in the application circuit operation. However, circumstances can arise where an applied voltage exceeds the operating voltage range of a given pin. If this condition occurs, there is a risk that some internal ESD protection circuits can turn on and conduct current. Any such current flow occurs through steering-diode paths and rarely involves the absorption device.
Figure 26 shows a specific example where the input voltage (VIN) exceeds the positive supply voltage (V+) by 500 mV or more. Much of what happens in the circuit depends on the supply characteristics. If V+ can sink the current, then one of the upper input steering diodes conducts and directs current to V+. Excessively high current levels can flow with increasingly higher VIN. As a result, the data sheet specifications recommend that applications limit the input current to 10 mA.
If the supply is not capable of sinking the current, VIN can begin sourcing current to the operational amplifier and then take over as the source of positive supply voltage. The danger in this case is that the voltage can rise to levels that exceed the operational amplifier absolute maximum ratings.
Another common question involves what happens to the amplifier if an input signal is applied to the input when the power supplies (V+ or V–) are at 0 V. Again, this question depends on the supply characteristic when at 0 V, or at a level below the input signal amplitude. If the supplies appear as high impedance, then the input source supplies the operational amplifier current through the current-steering diodes. This state is not a normal bias condition; most likely, the amplifier does not operate normally. If the supplies are low impedance, then the current through the steering diodes can become quite high. The current level depends on the ability of the input source to deliver current and any resistance in the input path.
If there is any uncertainty about the ability of the supply to absorb this current, add external Zener diodes to the supply pins; see Figure 26. Select the Zener voltage so that the diode does not turn on during normal operation. However, the Zener voltage must be low enough so that the Zener diode conducts if the supply pin begins to rise above the safe-operating, supply-voltage level.
The input pins of the TLVx172 are protected from excessive differential voltage with back-to-back diodes; see Figure 26. In most circuit applications, the input protection circuitry has no effect. However, in low-gain or G = 1 circuits, fast-ramping input signals can forward-bias these diodes because the output of the amplifier cannot respond rapidly enough to the input ramp. If the input signal is fast enough to create this forward-bias condition, then limit the input signal current to 10 mA or less. If the input signal current is not inherently limited, an input series resistor can limit the input signal current. This input series resistor degrades the low-noise performance of the TLVx172. Figure 26 shows an example configuration that implements a current-limiting feedback resistor.
The dynamic characteristics of the TLVx172 are optimized for common operating conditions. The combination of low closed-loop gain and high capacitive loads decreases the phase margin of the amplifier and can lead to gain peaking or oscillations. As a result, heavier capacitive loads must be isolated from the output. The simplest way to achieve this isolation is to add a small resistor (for example, ROUT equal to 50 Ω) in series with the output. Figure 27 and Figure 28 show graphs of small-signal overshoot versus capacitive load for several values of ROUT. See the Feedback Plots Define Op Amp AC Performance application note for details of analysis techniques and application circuits.
100-mV output step, G = –1 |
100-mV output step, G = 1 |
The input common-mode voltage range of the TLVx172 device extends 100 mV below the negative rail and within 2 V of the top rail for normal operation.
This device can operate with full rail-to-rail input 100 mV beyond the top rail, but with reduced performance within 2 V of the top rail. Table 2 lists the typical performances in this range.
PARAMETER | MIN | TYP | MAX | UNIT |
---|---|---|---|---|
Input common-mode voltage | (V+) – 2 | (V+) + 0.1 | V | |
Offset voltage | 7 | mV | ||
Offset voltage vs temperature | 12 | µV/°C | ||
Common-mode rejection | 65 | dB | ||
Open-loop gain | 60 | dB | ||
Gain-bandwidth product | 0.3 | MHz | ||
Slew rate | 0.3 | V/µs |
Overload recovery is defined as the time required for the operational amplifier output to recover from the saturated state to the linear state. The output devices of the operational amplifier enter the saturation region when the output voltage exceeds the rated operating voltage, which is a result from the high input voltage or the high gain. After the device enters the saturation region, the charge carriers in the output devices require time to return back to the normal state. After the charge carriers return back to the equilibrium state, the device begins to slew at the normal slew rate. As a result, the propagation delay in case of an overload condition is the sum of the overload recovery time and the slew time. The overload recovery time for the TLVx172 is approximately 2 µs.
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The TLVx172 operational amplifier provides high overall performance in a large number of general-purpose applications. As with all amplifiers, applications with noisy or high-impedance power supplies require decoupling capacitors placed close to the device pins. In most cases, 0.1-µF capacitors are adequate. Follow the additional recommendations in the Layout Guidelines section to achieve the maximum performance from this device. Many applications introduce capacitive loading to the output of the amplifier (which potentially causes instability). To stabilize the amplifier, add an isolation resistor between the amplifier output and the capacitive load. Typical Application section shows the process for selecting a resistor.
This circuit can drive capacitive loads (such as cable shields, reference buffers, MOSFET gates, and diodes). The circuit uses an isolation resistor (RISO) to stabilize the output of an operational amplifier. RISO modifies the open-loop gain of the system to ensure that the circuit has sufficient phase margin.
The design requirements are:
Figure 29 shows a unity-gain buffer driving a capacitive load. Equation 1 shows the transfer function for the circuit in Figure 29.Figure 29 does not show the open-loop output resistance of the operational amplifier (Ro).
The transfer function in Equation 1 has a pole and a zero. The frequency of the pole (fp) is determined by (Ro + RISO) and CLOAD. The RISO and CLOAD components determine the frequency of the zero (fz). A stable system is obtained by selecting RISO so that the rate of closure (ROC) between the open-loop gain (AOL) and 1/β is 20 dB per decade. Figure 30 shows the concept. The 1/β curve for a unity-gain buffer is 0 dB.
Typically, ROC stability analysis is simulated. The validity of the analysis depends on multiple factors, especially the accurate modeling of Ro. In addition to simulating the ROC, a robust stability analysis includes a measurement of overshoot percentage and AC gain peaking of the circuit using a function generator, oscilloscope, and gain and phase analyzer. Phase margin is then calculated from these measurements. Table 3 shows the overshoot percentage and AC gain peaking that correspond to phase margins of 45° and 60°. For more details on this design and other alternative devices that can replace the TLVx172, see the Capacitive Load Drive Solution Using an Isolation Resistor precision design.
PHASE MARGIN | OVERSHOOT | AC GAIN PEAKING |
---|---|---|
45° | 23.3% | 2.35 dB |
60° | 8.8% | 0.28 dB |
The values of RISO that yield phase margins of 45º and 60º for various capacitive loads are determined using the described methodology. Figure 31 shows the results.
The TLVx172 is specified for operation from 4.5 V to 36 V (±2.25 V to ±18 V); many specifications apply from –40°C to +125°C. Parameters that can exhibit significant variance with regard to operating voltage or temperature are shown in the Typical Characteristics section.
CAUTION
Supply voltages larger than 40 V can permanently damage the device; see the Absolute Maximum Ratings table.
Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-impedance power supplies. For more detailed information on bypass capacitor placement, see the Layout section.
For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:
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NOTE
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NOTE
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PARTS | PRODUCT FOLDER | ORDER NOW | TECHNICAL DOCUMENTS | TOOLS & SOFTWARE | SUPPORT & COMMUNITY |
---|---|---|---|---|---|
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