SGLS008G March   2003  – February 2018 TLV2460A-Q1 , TLV2461A-Q1 , TLV2462-Q1 , TLV2462A-Q1 , TLV2463A-Q1 , TLV2464A-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Typical Application
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
    2.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information: TLV2460x-Q1
    5. 6.5  Thermal Information: TLV2461x-Q1
    6. 6.6  Thermal Information: TLV2462-Q1
    7. 6.7  Thermal Information: TLV2462A-Q1
    8. 6.8  Thermal Information: TLV2463x-Q1
    9. 6.9  Electrical Characteristics: VDD = 3 V
    10. 6.10 Electrical Characteristics: VDD = 5 V
    11. 6.11 Operating Characteristics: VDD = 3 V
    12. 6.12 Operating Characteristics: VDD = 5 V
    13. 6.13 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Driving a Capacitive Load
      2. 8.3.2 Offset Voltage
      3. 8.3.3 General Configurations
      4. 8.3.4 General Power Dissipation Considerations
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Function
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Macromodel Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|8
  • DGK|8
  • PW|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

TLV2460-Q1, TLV2460A-Q1 PW Package
8-Pin TSSOP
Top View
TLV2460-Q1 TLV2460A-Q1 TLV2461-Q1 TLV2461A-Q1 TLV2462-Q1 TLV2462A-Q1 TLV2463-Q1 TLV2463A-Q1 TLV2464A-Q1 po_gls008.gif
NC- no internal connection
TLV2461-Q1, TLV2461A-Q1 PW Package
8-Pin TSSOP
Top View
TLV2460-Q1 TLV2460A-Q1 TLV2461-Q1 TLV2461A-Q1 TLV2462-Q1 TLV2462A-Q1 TLV2463-Q1 TLV2463A-Q1 TLV2464A-Q1 po_861_gls008.gif
NC- no internal connection
TLV2462-Q1, TLV2462A-Q1 D, DGK, or PW Package
8-Pin SOIC, TSSOP, or VSSOP
Top View
TLV2460-Q1 TLV2460A-Q1 TLV2461-Q1 TLV2461A-Q1 TLV2462-Q1 TLV2462A-Q1 TLV2463-Q1 TLV2463A-Q1 TLV2464A-Q1 po_862_gls008.gif
NC – No internal connection

Pin Functions

PINI/ODESCRIPTION
NAMETLV2460-Q1,
TLV2460A-Q1		TLV2461-Q1,
TLV2461A-Q1		TLV2462-Q1,
TLV2462A-Q1
1IN — — 2 I Inverting input, channel 1
1IN+ — — 3 I Noninverting input, channel 1
1OUT — — 1 O Output, channel 1
2IN — — 6 I Inverting input, channel 2
2IN+ — — 5 I Noninverting input, channel 2
2OUT — — 7 O Output, channel 2
IN 2 2 — I Inverting input
IN+ 3 3 — I Noninverting input
GND 4 4 4 — Negative (lowest) supply
NC 1, 5 1, 5, 8 — — No internal connection
OUT 6 6 — O Output
SHDN 8 — — I Shutdown
VDD+ 7 7 8 — Positive (highest) supply
TLV2463-Q1, TLV2463A-Q1 PW Package
14-Pin TSSOP
Top View
TLV2460-Q1 TLV2460A-Q1 TLV2461-Q1 TLV2461A-Q1 TLV2462-Q1 TLV2462A-Q1 TLV2463-Q1 TLV2463A-Q1 TLV2464A-Q1 po_14pin63_gls008.gif
NC – No internal connection
TLV2463-Q1, TLV2463A-Q1 PW Package
14-Pin TSSOP
Top View
TLV2460-Q1 TLV2460A-Q1 TLV2461-Q1 TLV2461A-Q1 TLV2462-Q1 TLV2462A-Q1 TLV2463-Q1 TLV2463A-Q1 TLV2464A-Q1 po_14pin64_gls008.gif

Pin Functions

PINI/ODESCRIPTION
NAMETLV2463-Q1, TLV2463A-Q1 TLV2464A-Q1
1IN 2 2 I Inverting input, channel 1
1IN+ 3 3 I Noninverting input, channel 1
1OUT 1 1 O Output, channel 1
1SHDN 6 — I Shutdown for channel 1
2IN 12 6 I Inverting input, channel 2
2IN+ 11 5 I Noninverting input, channel 2
2OUT 13 7 O Output, channel 2
2SHDN 9 — I Shutdown for channel 2
3N — 9 I Inverting input, channel 3
3IN+ — 10 I Noninverting input, channel 3
3OUT — 8 O Output, channel 3
4IN — 13 I Inverting input, channel 4
4IN+ — 12 I Noninverting input, channel 4
4OUT — 14 O Output, channel 4
IN — — I Inverting input
IN+ — — I Noninverting input
GND 4 11 — Negative (lowest) supply
NC 5, 7, 8, 10 — — No internal connection
OUT — — O Output
SHDN — — I Shutdown
VDD+ 14 4 — Positive (highest) supply