SBAS906 Data sheet

SBAS906 March 2018 TLV320ADC3100

PRODUCTION DATA.

Package Options

Mechanical Data (Package|Pins)

RGE|24
- MPQF124G

Thermal pad, mechanical data (Package|Pins)

RGE|24
- QFND008AA

Orderable Information

8.3.6 Audio Clock Generation

The audio converters in the fully programmable filter mode of the TLV320ADC3100 require an internal audio master clock at a frequency of ≥ N × f_S, where N = IADC (page 0, register 21) when filter mode (page 0, register 61) equals zero; otherwise, N equals the instruction count from the ADC processing blocks (see Table 6). The master clock is obtained from an external clock signal applied to the device.

The device can accept an MCLK input from 512 kHz to 50 MHz, which can then be passed through either a programmable divider or a PLL to get the proper internal audio master clock required by the device. The BCLK input can also be used to generate the internal audio master clock.

A primary concern is proper operation of the TLV320ADC3100 at various sample rates with the limited MCLK frequencies available in the system. This device includes a programmable PLL to accommodate such situations. The integrated PLL can generate audio clocks from a wide variety of possible MCLK inputs, with particular focus paid to the standard MCLK rates already widely used.

When the PLL is enabled:

Equation 1. f_S = (PLLCLK_IN × K × R) / (NADC × MADC × AOSR × P)

where

P = 1, 2, 3,…, 8
R = 1, 2, …, 16
K = J.D
J = 1, 2, 3, …, 63
D = 0000, 0001, 0002, 0003, …, 9998, 9999
PLLCLK_IN can be MCLK or BCLK, selected by page 0, register 4, bits 3:2

P, R, J, and D are register programmable. J is the integer portion of K (the numbers to the left of the decimal point), whereas D is the fractional portion of K (the numbers to the right of the decimal point, assuming four digits of precision).

Examples:

If K = 8.5, then J = 8, D = 5000
If K = 7.12, then J = 7, D = 1200
If K = 14.03, then J = 14, D = 0300
If K = 6.0004, then J = 6, D = 0004

When the PLL is enabled and D = 0000, the following conditions must be satisfied to meet specified performance:

512 kHz ≤ (PLLCLK_IN / P) ≤ 20 MHz
80 MHz ≤ (PLLCLK _IN × K × R / P) ≤ 110 MHz
4 ≤ J ≤ 55

When the PLL is enabled and D ≠ 0000, the following conditions must be satisfied to meet specified performance:

10 MHz ≤ PLLCLK _IN / P ≤ 20 MHz
80 MHz ≤ PLLCLK _IN × K × R / P ≤ 110 MHz
4 ≤ J ≤ 11
R = 1

Example:

For MCLK = 12 MHz, f_S = 44.1 kHz, NADC = 8, MADC = 2, and AOSR = 128:
Select P = 1, R = 1, K = 7.5264, which results in J = 7, D = 5264

Example:

For MCLK = 12 MHz, f_S = 48 kHz , NADC = 8, MADC = 2, and AOSR = 128:
Select P = 1, R = 1, K = 8.192, which results in J = 8, D = 1920

Table 1 lists several example cases of typical MCLK rates and how to program the PLL to achieve sample rates of f_S = 44.1 kHz or 48 kHz with NADC = 8, MADC = 2, and AOSR = 128.

Table 1. Typical MCLK Rates

MCLK (MHz)	P	R	J	D	ACHIEVED f_S	% ERROR
f_S = 44.1 kHz
2.8224	1	1	32	0	44,100.00	0.0000
5.6448	1	1	16	0	44,100.00	0.0000
12.0	1	1	7	5264	44,100.00	0.0000
13.0	1	1	6	9474	44,099.71	–0.0007
16.0	1	1	5	6448	44,100.00	0.0000
19.2	1	1	4	7040	44,100.00	0.0000
19.68	1	1	4	5893	44,100.30	0.0007
48.0	4	1	7	5264	44,100.00	0.0000
f_S = 48 kHz
2.048	1	1	48	0	48,000.00	0.0000
3.072	1	1	32	0	48,000.00	0.0000
4.096	1	1	24	0	48,000.00	0.0000
6.144	1	1	16	0	48,000.00	0.0000
8.192	1	1	12	0	48,000.00	0.0000
12.0	1	1	8	1920	48,000.00	0.0000
13.0	1	1	7	5618	47,999.71	–0.0006
16.0	1	1	6	1440	48,000.00	0.0000
19.2	1	1	5	1200	48,000.00	0.0000
19.68	1	1	4	9951	47,999.79	–0.0004
48.0	4	1	8	1920	48,000.00	0.0000

Figure 27 shows a detailed diagram of the audio clock section of the TLV320ADC3100.

NOTE:

MADC × AOSR ≥ IADC, where IADC is the number of instructions (instruction count) for the ADC MAC engine. IADC is programmable from 2, 4,…, 510. The convention used in this figure is page number: register number (reset value).

Figure 27. Audio Clock Generation Processing