SBAS906 March 2018 TLV320ADC3100
PRODUCTION DATA.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved | Reserved | Reserved | Reserved | BCLK_INVERT | BWCLK_PWR codec inactive | BDIV_CLKIN | |
R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-0h | R/W-10h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:4 | Reserved | R/W | 0h | Reserved. Do not write any value other than reset value. |
3 | BCLK_INVERT | R/W | 0h | 0: BCLK is not inverted (valid for both primary and secondary BCLK)
1: BCLK is inverted (valid for both primary and secondary BCLK) |
2 | BWCLK_PWR codec inactive | R/W | 0h | 0: BCLK and WCLK are active even with the codec powered down: disabled (valid for both primary and secondary BCLK)
1: BCLK and WCLK are active even with the codec powered down: enabled (valid for both primary and secondary BCLK) |
1:0 | BDIV_CLKIN | R/W | 10h | 00: Reserved. Do not use.
01: Reserved. Do not use. 10: BDIV_CLKIN = ADC_CLK (generated on-chip) 11: BDIV_CLKIN = ADC_MOD_CLK (generated on-chip) |