SBAS992A
July 2019 – October 2019
TLV320ADC6140
PRODUCTION DATA.
1
Features
2
Applications
3
Description
Simplified Block Diagram
4
Revision History
5
Device Comparison Table
6
Pin Configuration and Functions
Pin Functions
7
Specifications
7.1
Absolute Maximum Ratings
7.2
ESD Ratings
7.3
Recommended Operating Conditions
7.4
Thermal Information
7.5
Electrical Characteristics
7.6
Timing Requirements: I2C Interface
7.7
Switching Characteristics: I2C Interface
7.8
Timing Requirements: SPI Interface
7.9
Switching Characteristics: SPI Interface
7.10
Timing Requirements: TDM, I2S or LJ Interface
7.11
Switching Characteristics: TDM, I2S or LJ Interface
7.12
Timing Requirements: PDM Digital Microphone Interface
7.13
Switching Characteristics: PDM Digial Microphone Interface
7.14
Typical Characteristics
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Serial Interfaces
8.3.1.1
Control Serial Interfaces
8.3.1.2
Audio Serial Interfaces
8.3.1.2.1
Time Division Multiplexed Audio (TDM) Interface
8.3.1.2.2
Inter IC Sound (I2S) Interface
8.3.1.2.3
Left-Justified (LJ) Interface
8.3.1.3
Using Multiple Devices With Shared Buses
8.3.2
Phase-Locked Loop (PLL) and Clock Generation
8.3.3
Input Channel Configurations
8.3.4
Reference Voltage
8.3.5
Programmable Microphone Bias
8.3.6
Signal-Chain Processing
8.3.6.1
Programmable Channel Gain and Digital Volume Control
8.3.6.2
Programmable Channel Gain Calibration
8.3.6.3
Programmable Channel Phase Calibration
8.3.6.4
Programmable Digital High-Pass Filter
8.3.6.5
Programmable Digital Biquad Filters
8.3.6.6
Programmable Channel Summer and Digital Mixer
8.3.6.7
Configurable Digital Decimation Filters
8.3.6.7.1
Linear Phase Filters
8.3.6.7.1.1
Sampling Rate: 8 kHz or 7.35 kHz
8.3.6.7.1.2
Sampling Rate: 16 kHz or 14.7 kHz
8.3.6.7.1.3
Sampling Rate: 24 kHz or 22.05 kHz
8.3.6.7.1.4
Sampling Rate: 32 kHz or 29.4 kHz
8.3.6.7.1.5
Sampling Rate: 48 kHz or 44.1 kHz
8.3.6.7.1.6
Sampling Rate: 96 kHz or 88.2 kHz
8.3.6.7.1.7
Sampling Rate: 192 kHz or 176.4 kHz
8.3.6.7.1.8
Sampling Rate: 384 kHz or 352.8 kHz
8.3.6.7.1.9
Sampling Rate 768 kHz or 705.6 kHz
8.3.6.7.2
Low-Latency Filters
8.3.6.7.2.1
Sampling Rate: 16 kHz or 14.7 kHz
8.3.6.7.2.2
Sampling Rate: 24 kHz or 22.05 kHz
8.3.6.7.2.3
Sampling Rate: 32 kHz or 29.4 kHz
8.3.6.7.2.4
Sampling Rate: 48 kHz or 44.1 kHz
8.3.6.7.2.5
Sampling Rate: 96 kHz or 88.2 kHz
8.3.6.7.2.6
Sampling Rate 192 kHz or 176.4 kHz
8.3.6.7.3
Ultra-Low-Latency Filters
8.3.6.7.3.1
Sampling Rate: 16 kHz or 14.7 kHz
8.3.6.7.3.2
Sampling Rate: 24 kHz or 22.05 kHz
8.3.6.7.3.3
Sampling Rate: 32 kHz or 29.4 kHz
8.3.6.7.3.4
Sampling Rate: 48 kHz or 44.1 kHz
8.3.6.7.3.5
Sampling Rate: 96 kHz or 88.2 kHz
8.3.6.7.3.6
Sampling Rate 192 kHz or 176.4 kHz
8.3.6.7.3.7
Sampling Rate 384 kHz or 352.8 kHz
8.3.7
Dynamic Range Enhancer (DRE)
8.3.8
Automatic Gain Controller (AGC)
8.3.9
Digital PDM Microphone Record Channel
8.3.10
Interrupts, Status, and Digital I/O Pin Multiplexing
8.4
Device Functional Modes
8.4.1
Hardware Shutdown
8.4.2
Sleep Mode or Software Shutdown
8.4.3
Active Mode
8.4.4
Software Reset
8.5
Programming
8.5.1
Control Serial Interfaces
8.5.1.1
I2C Control Interface
8.5.1.1.1
General I2C Operation
8.5.1.1.2
I2C Single-Byte and Multiple-Byte Transfers
8.5.1.1.2.1
I2C Single-Byte Write
8.5.1.1.2.2
I2C Multiple-Byte Write
8.5.1.1.2.3
I2C Single-Byte Read
8.5.1.1.2.4
I2C Multiple-Byte Read
8.5.1.2
SPI Control Interface
Table 1.
SPI Command Word
8.6
Register Maps
8.6.1
Device Configuration Registers
8.6.1.1
Register Descriptions
8.6.1.1.1
PAGE_CFG Register (page = 0x00, address = 0x00) [reset = 0h]
Table 53.
PAGE_CFG Register Field Descriptions
8.6.1.1.2
SW_RESET Register (page = 0x00, address = 0x01) [reset = 0h]
Table 54.
SW_RESET Register Field Descriptions
8.6.1.1.3
SLEEP_CFG Register (page = 0x00, address = 0x02) [reset = 0h]
Table 55.
SLEEP_CFG Register Field Descriptions
8.6.1.1.4
SHDN_CFG Register (page = 0x00, address = 0x05) [reset = 5h]
Table 56.
SHDN_CFG Register Field Descriptions
8.6.1.1.5
ASI_CFG0 Register (page = 0x00, address = 0x07) [reset = 30h]
Table 57.
ASI_CFG0 Register Field Descriptions
8.6.1.1.6
ASI_CFG1 Register (page = 0x00, address = 0x08) [reset = 0h]
Table 58.
ASI_CFG1 Register Field Descriptions
8.6.1.1.7
ASI_CFG2 Register (page = 0x00, address = 0x09) [reset = 0h]
Table 59.
ASI_CFG2 Register Field Descriptions
8.6.1.1.8
ASI_CH1 Register (page = 0x00, address = 0x0B) [reset = 0h]
Table 60.
ASI_CH1 Register Field Descriptions
8.6.1.1.9
ASI_CH2 Register (page = 0x00, address = 0x0C) [reset = 1h]
Table 61.
ASI_CH2 Register Field Descriptions
8.6.1.1.10
ASI_CH3 Register (page = 0x00, address = 0x0D) [reset = 2h]
Table 62.
ASI_CH3 Register Field Descriptions
8.6.1.1.11
ASI_CH4 Register (page = 0x00, address = 0x0E) [reset = 3h]
Table 63.
ASI_CH4 Register Field Descriptions
8.6.1.1.12
ASI_CH5 Register (page = 0x00, address = 0x0F) [reset = 4h]
Table 64.
ASI_CH5 Register Field Descriptions
8.6.1.1.13
ASI_CH6 Register (page = 0x00, address = 0x10) [reset = 5h]
Table 65.
ASI_CH6 Register Field Descriptions
8.6.1.1.14
ASI_CH7 Register (page = 0x00, address = 0x11) [reset = 6h]
Table 66.
ASI_CH7 Register Field Descriptions
8.6.1.1.15
ASI_CH8 Register (page = 0x00, address = 0x12) [reset = 7h]
Table 67.
ASI_CH8 Register Field Descriptions
8.6.1.1.16
MST_CFG0 Register (page = 0x00, address = 0x13) [reset = 2h]
Table 68.
MST_CFG0 Register Field Descriptions
8.6.1.1.17
MST_CFG1 Register (page = 0x00, address = 0x14) [reset = 48h]
Table 69.
MST_CFG1 Register Field Descriptions
8.6.1.1.18
ASI_STS Register (page = 0x00, address = 0x15) [reset = FFh]
Table 70.
ASI_STS Register Field Descriptions
8.6.1.1.19
CLK_SRC Register (page = 0x00, address = 0x16) [reset = 10h]
Table 71.
CLK_SRC Register Field Descriptions
8.6.1.1.20
PDMCLK_CFG Register (page = 0x00, address = 0x1F) [reset = 40h]
Table 72.
PDMCLK_CFG Register Field Descriptions
8.6.1.1.21
PDMIN_CFG Register (page = 0x00, address = 0x20) [reset = 0h]
Table 73.
PDMIN_CFG Register Field Descriptions
8.6.1.1.22
GPIO_CFG0 Register (page = 0x00, address = 0x21) [reset = 22h]
Table 74.
GPIO_CFG0 Register Field Descriptions
8.6.1.1.23
GPO_CFG0 Register (page = 0x00, address = 0x22) [reset = 0h]
Table 75.
GPO_CFG0 Register Field Descriptions
8.6.1.1.24
GPO_CFG1 Register (page = 0x00, address = 0x23) [reset = 0h]
Table 76.
GPO_CFG1 Register Field Descriptions
8.6.1.1.25
GPO_CFG2 Register (page = 0x00, address = 0x24) [reset = 0h]
Table 77.
GPO_CFG2 Register Field Descriptions
8.6.1.1.26
GPO_CFG3 Register (page = 0x00, address = 0x25) [reset = 0h]
Table 78.
GPO_CFG3 Register Field Descriptions
8.6.1.1.27
GPO_VAL Register (page = 0x00, address = 0x29) [reset = 0h]
Table 79.
GPO_VAL Register Field Descriptions
8.6.1.1.28
GPIO_MON Register (page = 0x00, address = 0x2A) [reset = 0h]
Table 80.
GPIO_MON Register Field Descriptions
8.6.1.1.29
GPI_CFG0 Register (page = 0x00, address = 0x2B) [reset = 0h]
Table 81.
GPI_CFG0 Register Field Descriptions
8.6.1.1.30
GPI_CFG1 Register (page = 0x00, address = 0x2C) [reset = 0h]
Table 82.
GPI_CFG1 Register Field Descriptions
8.6.1.1.31
GPI_MON Register (page = 0x00, address = 0x2F) [reset = 0h]
Table 83.
GPI_MON Register Field Descriptions
8.6.1.1.32
INT_CFG Register (page = 0x00, address = 0x32) [reset = 0h]
Table 84.
INT_CFG Register Field Descriptions
8.6.1.1.33
INT_MASK0 Register (page = 0x00, address = 0x33) [reset = FFh]
Table 85.
INT_MASK0 Register Field Descriptions
8.6.1.1.34
INT_LTCH0 Register (page = 0x00, address = 0x36) [reset = 0h]
Table 86.
INT_LTCH0 Register Field Descriptions
8.6.1.1.35
BIAS_CFG Register (page = 0x00, address = 0x3B) [reset = 0h]
Table 87.
BIAS_CFG Register Field Descriptions
8.6.1.1.36
CH1_CFG0 Register (page = 0x00, address = 0x3C) [reset = 0h]
Table 88.
CH1_CFG0 Register Field Descriptions
8.6.1.1.37
CH1_CFG1 Register (page = 0x00, address = 0x3D) [reset = 0h]
Table 89.
CH1_CFG1 Register Field Descriptions
8.6.1.1.38
CH1_CFG2 Register (page = 0x00, address = 0x3E) [reset = C9h]
Table 90.
CH1_CFG2 Register Field Descriptions
8.6.1.1.39
CH1_CFG3 Register (page = 0x00, address = 0x3F) [reset = 80h]
Table 91.
CH1_CFG3 Register Field Descriptions
8.6.1.1.40
CH1_CFG4 Register (page = 0x00, address = 0x40) [reset = 0h]
Table 92.
CH1_CFG4 Register Field Descriptions
8.6.1.1.41
CH2_CFG0 Register (page = 0x00, address = 0x41) [reset = 0h]
Table 93.
CH2_CFG0 Register Field Descriptions
8.6.1.1.42
CH2_CFG1 Register (page = 0x00, address = 0x42) [reset = 0h]
Table 94.
CH2_CFG1 Register Field Descriptions
8.6.1.1.43
CH2_CFG2 Register (page = 0x00, address = 0x43) [reset = C9h]
Table 95.
CH2_CFG2 Register Field Descriptions
8.6.1.1.44
CH2_CFG3 Register (page = 0x00, address = 0x44) [reset = 80h]
Table 96.
CH2_CFG3 Register Field Descriptions
8.6.1.1.45
CH2_CFG4 Register (page = 0x00, address = 0x45) [reset = 0h]
Table 97.
CH2_CFG4 Register Field Descriptions
8.6.1.1.46
CH3_CFG0 Register (page = 0x00, address = 0x46) [reset = 0h]
Table 98.
CH3_CFG0 Register Field Descriptions
8.6.1.1.47
CH3_CFG1 Register (page = 0x00, address = 0x47) [reset = 0h]
Table 99.
CH3_CFG1 Register Field Descriptions
8.6.1.1.48
CH3_CFG2 Register (page = 0x00, address = 0x48) [reset = C9h]
Table 100.
CH3_CFG2 Register Field Descriptions
8.6.1.1.49
CH3_CFG3 Register (page = 0x00, address = 0x49) [reset = 80h]
Table 101.
CH3_CFG3 Register Field Descriptions
8.6.1.1.50
CH3_CFG4 Register (page = 0x00, address = 0x4A) [reset = 0h]
Table 102.
CH3_CFG4 Register Field Descriptions
8.6.1.1.51
CH4_CFG0 Register (page = 0x00, address = 0x4B) [reset = 0h]
Table 103.
CH4_CFG0 Register Field Descriptions
8.6.1.1.52
CH4_CFG1 Register (page = 0x00, address = 0x4C) [reset = 0h]
Table 104.
CH4_CFG1 Register Field Descriptions
8.6.1.1.53
CH4_CFG2 Register (page = 0x00, address = 0x4D) [reset = C9h]
Table 105.
CH4_CFG2 Register Field Descriptions
8.6.1.1.54
CH4_CFG3 Register (page = 0x00, address = 0x4E) [reset = 80h]
Table 106.
CH4_CFG3 Register Field Descriptions
8.6.1.1.55
CH4_CFG4 Register (page = 0x00, address = 0x4F) [reset = 0h]
Table 107.
CH4_CFG4 Register Field Descriptions
8.6.1.1.56
CH5_CFG2 Register (page = 0x00, address = 0x52) [reset = C9h]
Table 108.
CH5_CFG2 Register Field Descriptions
8.6.1.1.57
CH5_CFG3 Register (page = 0x00, address = 0x53) [reset = 80h]
Table 109.
CH5_CFG3 Register Field Descriptions
8.6.1.1.58
CH5_CFG4 Register (page = 0x00, address = 0x54) [reset = 0h]
Table 110.
CH5_CFG4 Register Field Descriptions
8.6.1.1.59
CH6_CFG2 Register (page = 0x00, address = 0x57) [reset = C9h]
Table 111.
CH6_CFG2 Register Field Descriptions
8.6.1.1.60
CH6_CFG3 Register (page = 0x00, address = 0x58) [reset = 80h]
Table 112.
CH6_CFG3 Register Field Descriptions
8.6.1.1.61
CH6_CFG4 Register (page = 0x00, address = 0x59) [reset = 0h]
Table 113.
CH6_CFG4 Register Field Descriptions
8.6.1.1.62
CH7_CFG2 Register (page = 0x00, address = 0x5C) [reset = C9h]
Table 114.
CH7_CFG2 Register Field Descriptions
8.6.1.1.63
CH7_CFG3 Register (page = 0x00, address = 0x5D) [reset = 80h]
Table 115.
CH7_CFG3 Register Field Descriptions
8.6.1.1.64
CH7_CFG4 Register (page = 0x00, address = 0x5E) [reset = 0h]
Table 116.
CH7_CFG4 Register Field Descriptions
8.6.1.1.65
CH8_CFG2 Register (page = 0x00, address = 0x61) [reset = C9h]
Table 117.
CH8_CFG2 Register Field Descriptions
8.6.1.1.66
CH8_CFG3 Register (page = 0x00, address = 0x62) [reset = 80h]
Table 118.
CH8_CFG3 Register Field Descriptions
8.6.1.1.67
CH8_CFG4 Register (page = 0x00, address = 0x63) [reset = 0h]
Table 119.
CH8_CFG4 Register Field Descriptions
8.6.1.1.68
DSP_CFG0 Register (page = 0x00, address = 0x6B) [reset = 1h]
Table 120.
DSP_CFG0 Register Field Descriptions
8.6.1.1.69
DSP_CFG1 Register (page = 0x00, address = 0x6C) [reset = 40h]
Table 121.
DSP_CFG1 Register Field Descriptions
8.6.1.1.70
DRE_CFG0 Register (page = 0x00, address = 0x6D) [reset = 7Bh]
Table 122.
DRE_CFG0 Register Field Descriptions
8.6.1.1.71
AGC_CFG0 Register (page = 0x00, address = 0x70) [reset = E7h]
Table 123.
AGC_CFG0 Register Field Descriptions
8.6.1.1.72
IN_CH_EN Register (page = 0x00, address = 0x73) [reset = F0h]
Table 124.
IN_CH_EN Register Field Descriptions
8.6.1.1.73
ASI_OUT_CH_EN Register (page = 0x00, address = 0x74) [reset = 0h]
Table 125.
ASI_OUT_CH_EN Register Field Descriptions
8.6.1.1.74
PWR_CFG Register (page = 0x00, address = 0x75) [reset = 0h]
Table 126.
PWR_CFG Register Field Descriptions
8.6.1.1.75
DEV_STS0 Register (page = 0x00, address = 0x76) [reset = 0h]
Table 127.
DEV_STS0 Register Field Descriptions
8.6.1.1.76
DEV_STS1 Register (page = 0x00, address = 0x77) [reset = 80h]
Table 128.
DEV_STS1 Register Field Descriptions
8.6.1.1.77
I2C_CKSUM Register (page = 0x00, address = 0x7E) [reset = 0h]
Table 129.
I2C_CKSUM Register Field Descriptions
8.6.2
Programmable Coefficient Registers
8.6.2.1
Programmable Coefficient Registers: Page = 0x02
8.6.2.2
Programmable Coefficient Registers: Page = 0x03
8.6.2.3
Programmable Coefficient Registers: Page = 0x04
9
Application and Implementation
9.1
Application Information
9.2
Typical Applications
9.2.1
Four-Channel Analog Microphone Recording
9.2.1.1
Design Requirements
9.2.1.2
Detailed Design Procedure
9.2.1.2.1
Example Device Register Configuration Script for EVM Setup
9.2.1.3
Application Curves
9.2.2
Eight-Channel Digital PDM Microphone Recording
9.2.2.1
Design Requirements
9.2.2.2
Detailed Design Procedure
9.2.2.2.1
Example Device Register Configuration Script for EVM Setup
9.3
What to Do and What Not to Do
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
11.2
Layout Example
12
Device and Documentation Support
12.1
Documentation Support
12.1.1
Related Documentation
12.2
Receiving Notification of Documentation Updates
12.3
Community Resources
12.4
Trademarks
12.5
Electrostatic Discharge Caution
12.6
Glossary
13
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
RTW|24
MPQF167C
Thermal pad, mechanical data (Package|Pins)
RTW|24
QFND125K
Orderable Information
sbas992a_oa
sbas992a_pm
8
Detailed Description