11.3.1 Hardware Reset

The TLV320AIC3101 requires a hardware reset after power up for proper operation. After all power supplies are at their specified values, the RESET pin must be driven low for at least 10 ns. If this reset sequence is not performed, the TLV320AIC3101 may not respond properly to register reads/writes.

11.3.2 Digital Audio Data Serial Interface

Audio data is transferred between the host processor and the TLV320AIC3101 via the digital audio data serial interface. The audio bus of the TLV320AIC3101 can be configured for left- or right-justified, I²S, DSP, or TDM modes of operation, where communication with standard telephony PCM interfaces is supported within the TDM mode. These modes are all MSB-first, with data width programmable as 16, 20, 24, or 32 bits. In addition, the word clock (WCLK) and bit clock (BCLK) can be independently configured in either master or slave mode, for flexible connectivity to a wide variety of processors.

The word clock (WCLK) is used to define the beginning of a frame, and may be programmed as either a pulse or a square-wave signal. The frequency of this clock corresponds to the selected ADC and DAC sampling frequencies.

The bit clock (BCLK) is used to clock in and out the digital audio data across the serial bus. When in master mode, this signal can be programmed in two further modes: continuous transfer mode, and 256-clock mode. In continuous transfer mode, only the minimal number of bit clocks needed to transfer the audio data are generated, so in general the number of bit clocks per frame is two times the data width. For example, if data width is chosen as 16 bits, then 32 bit clocks are generated per frame. If the bit clock signal in master mode is to be used by a PLL in another device, it is recommended that the 16-bit or 32-bit data-width selections be used. These cases result in a low-jitter bit clock signal being generated, having frequencies of 32 f_S or 64 f_S. In the cases of 20-bit and 24-bt data width in master mode, the bit clocks generated in each frame are not all of equal period, due to the device not having a clean 40-f_S or 48-f_S clock signal readily available. The average frequency of the bit clock signal is still accurate in these cases (being 40 f_S or 48 f_S), but the resulting clock signal has higher jitter than in the 16-bit and 32-bit cases.

In 256-clock mode, a constant 256 bit clocks per frame are generated, independent of the data width chosen. The TLV320AIC3101 further includes programmability to place the DOUT line in the high-impedance state during all bit clocks when valid data is not being sent. By combining this capability with the ability to program at what bit clock in a frame the audio data begins, time-division multiplexing (TDM) can be accomplished, resulting in multiple codecs able to use a single audio serial data bus.

When the digital audio data serial interface is powered down while configured in master mode, the pins associated with the interface are put into a high-impedance state.

11.3.2.1 Right-Justified Mode

In right-justified mode, the LSB of the left channel is valid on the rising edge of the bit clock preceding the falling edge of word clock. Similarly, the LSB of the right channel is valid on the rising edge of the bit clock preceding the rising edge of the word clock.

Figure 12. Right-Justified Serial Data Bus Mode Operation

11.3.2.2 Left-Justified Mode

In left-justified mode, the MSB of the right channel is valid on the rising edge of the bit clock following the falling edge of the word clock. Similarly, the MSB of the left channel is valid on the rising edge of the bit clock following the rising edge of the word clock.

Figure 13. Left-Justified Serial Data Bus Mode Operation

11.3.2.3 I²S Mode

In I²S mode, the MSB of the left channel is valid on the second rising edge of the bit clock after the falling edge of the word clock. Similarly, the MSB of the right channel is valid on the second rising edge of the bit clock after the rising edge of the word clock.

Figure 14. I²S Serial Data Bus Mode Operation

11.3.2.4 DSP Mode

In DSP mode, the rising edge of the word clock starts the data transfer with the left-channel data first, immediately followed by the right-channel data. Each data bit is valid on the falling edge of the bit clock.

Figure 15. DSP Serial Data Bus Mode Operation

11.3.2.5 TDM Data Transfer

Time-division multiplexed data transfer can be realized in any of the left- transfer modes if the 256-clock bit-clock mode is selected, although it is recommended to be used in either left-justified mode or DSP mode. By changing the programmable offset, the bit clock in each frame where the data begins can be changed, and the serial data output driver (DOUT) can also be programmed to the high-impedance state during all bit clocks except when valid data is being put onto the bus. This allows other codecs to be programmed with different offsets and to drive their data onto the same DOUT line, just in a different slot. For incoming data, the codec simply ignores data on the bus except where it is expected, based on the programmed offset.

Note that the location of the data when an offset is programmed is different, depending on what transfer mode is selected. In DSP mode, both left and right channels of data are transferred immediately adjacent to each other in the frame. This differs from left-justified mode, where the left- and right-channel data are always a half-frame apart in each frame. In this case, as the offset is programmed from zero to some higher value, both the left- and right-channel data move across the frame, but still stay a full half-frame apart from each other. This is depicted in Figure 16 for the two cases.

Figure 16. DSP Mode and Left-Justified Mode, Showing the
Effect of a Programmed Data-Word Offset

11.3.3 Audio Data Converters

The TLV320AIC3101 supports the following standard audio sampling rates: 8 kHz, 11.025 kHz, 12 kHz, 16 kHz, 22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, and 96 kHz. The converters also can operate at different sampling rates in various combinations, which are described further as follows.

The data converters are based on the concept of an f_S(ref) rate that is used internal to the part, and it is related to the actual sampling rates of the converters through a series of ratios. For typical sampling rates, f_S(ref) is either 44.1 kHz or 48 kHz, although it can realistically be set over a wider range of rates up to 53 kHz, with additional restrictions applying if the PLL is used. This concept is used to set the sampling rates of the ADC and DAC, and also to enable high-quality playback of low-sampling-rate data, without high-frequency audible noise being generated.

The sampling rate of the ADC and DAC can be set to f_S(ref)/NCODEC or 2 × f_S(ref)/NCODEC, with NCODEC being 1, 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, or 6 for both the NDAC and NADC settings. In the TLV320AIC3101, NDAC and NADC must be set to the same value, as the device only supports a common sample rate for the ADC and DAC channels. Therefore NCODEC = NDAC = NADC, and this is programmed by setting the value of bits D7–D4 equal to the value of bits D3–D0 in register 2, on page 0.

11.3.3.1 Audio Clock Generation

The audio converters in the TLV320AIC3101 need an internal audio master clock at a frequency of 256 f_S(ref), which can be obtained in a variety of manners from an external clock signal applied to the device.

A more detailed diagram of the audio clock section of the TLV320AIC3101 is shown in Figure 17.

Figure 17. Audio Clock Generation Processing

The device can accept an MCLK input from 512 kHz to 50 MHz, which can then be passed through either a programmable divider or a PLL to get the proper internal audio master clock required by the device. The BCLK input can also be used to generate the internal audio master clock.

A primary concern is proper operation of the codec at various sample rates with the limited MCLK frequencies available in the system. This device includes a highly programmable PLL to accommodate such situations easily. The integrated PLL can generate audio clocks from a wide variety of possible MCLK inputs, with particular focus paid to the standard MCLK rates already widely used.

When the PLL is disabled,

f_S(ref) = CLKDIV_IN/(128 × Q)

Where Q = 2, 3, …, 17

CLKDIV_IN can be MCLK or BCLK, selected by register 102, bits D7–D6.

NOTE – when NCODEC = 1.5, 2.5, 3.5, 4.5, or 5.5, odd values of Q are not allowed. In this mode, MCLK can be as high as 50 MHz, and f_S(ref) should fall within 39 kHz to 53 kHz, inclusive.

When the PLL is enabled,

f_S(ref) = (PLLCLK_IN × K × R)/(2048 × P), where

P = 1, 2, 3,…, 8
R = 1, 2, …, 16
K = J.D
J = 1, 2, 3, …, 63
D = 0000, 0001, 0002, 0003, …, 9998, 9999
PLLCLK_IN can be MCLK or BCLK, selected by Page 0, register 102, bits D5–D4

P, R, J, and D are register programmable. J is the integer portion of K (the numbers to the left of the decimal point), while D is the fractional portion of K (the numbers to the right of the decimal point, assuming four digits of precision).

Examples:

If K = 8.5, then J = 8, D = 5000
If K = 7.12, then J = 7, D = 1200
If K = 14.03, then J = 14, D = 0300
If K = 6.0004, then J = 6, D = 0004

When the PLL is enabled and D = 0000, the following conditions must be satisfied to meet specified performance:

2 MHz ≤ ( PLLCLK_IN/P ) ≤ 20 MHz
80 MHz ≤ (PLLCLK _IN × K × R/P ) ≤ 110 MHz
4 ≤ J ≤ 55

When the PLL is enabled and D≠0000, the following conditions must be satisfied to meet specified performance:

10 MHz ≤ PLLCLK _IN/P ≤ 20 MHz
80 MHz ≤ PLLCLK _IN × K × R/P ≤ 110 MHz
4 ≤ J ≤ 11
R = 1

Example:

MCLK = 12 MHz and f_S(ref) = 44.1 kHz
Select P = 1, R = 1, K = 7.5264, which results in J = 7, D = 5264

Example:

MCLK = 12 MHz and f_S(ref) = 48 kHz
Select P = 1, R = 1, K = 8.192, which results in J = 8, D = 1920

Table 1 lists several example cases of typical MCLK rates, and how to program the PLL to achieve f_S(ref) = 44.1 kHz or 48 kHz.

Table 1. Typical MCLK Rates

fS(ref) = 44.1 kHz
MCLK (MHz)	P	R	J	D	ACHIEVED fS(ref)	% ERROR
2.8224	1	1	32	0	44,100	0
5.6448	1	1	16	0	44,100	0
12	1	1	7	5264	44,100	0
13	1	1	6	9474	44,099.71	–0.0007
16	1	1	5	6448	44,100	0
19.2	1	1	4	7040	44,100	0
19.68	1	1	4	5893	44,100.3	0.0007
48	4	1	7	5264	44,100	0
fS(ref) = 48 kHz
MCLK (MHz)	P	R	J	D	ACHIEVED fS(ref)	% ERROR
2.048	1	1	48	0	48,000	0
3.072	1	1	32	0	48,000	0
4.096	1	1	24	0	48,000	0
6.144	1	1	16	0	48,000	0
8.192	1	1	12	0	48,000	0
12	1	1	8	1920	48,000	0
13	1	1	7	5618	47,999.71	–0.0006
16	1	1	6	1440	48,000	0
19.2	1	1	5	1200	48,000	0
19.68	1	1	4	9951	47,999.79	–0.0004
48	4	1	8	1920	48,000	0

11.3.3.2 Stereo Audio ADC

The TLV320AIC3101 includes a stereo audio ADC, which uses a delta-sigma modulator with 128-times oversampling in single-rate mode, followed by a digital decimation filter. The ADC supports sampling rates from 8 kHz to 48 kHz in single-rate mode, and up to 96 kHz in dual-rate mode. Whenever the ADC or DAC is in operation, the device requires that an audio master clock be provided and appropriate audio clock generation be set up within the device.

In order to provide optimal system power dissipation, the stereo ADC can be powered one channel at a time, to support the case where only mono record capability is required. In addition, both channels can be fully powered or entirely powered down.

The integrated digital decimation filter removes high-frequency content and downsamples the audio data from an initial sampling rate of 128 f_S to the final output sampling rate of f_S. The decimation filter provides a linear phase output response with a group delay of 17/f_S. The –3-dB bandwidth of the decimation filter extends to 0.45 f_S and scales with the sample rate (fS). The filter has minimum 75-dB attenuation over the stop band from 0.55 f_S to 64 f_S. Independent digital high-pass filters are also included with each ADC channel, with a corner frequency that can be independently set.

Because of the oversampling nature of the audio ADC and the integrated digital decimation filtering, requirements for analog antialiasing filtering are very relaxed. The TLV320AIC3101 integrates a second-order analog antialiasing filter with 20-dB attenuation at 1 MHz. This filter, combined with the digital decimation filter, provides sufficient antialiasing filtering without requiring additional external components.

The ADC is preceded by a programmable gain amplifier (PGA), which allows analog gain control from 0 dB to 59.5 dB in steps of 0.5 dB. The PGA gain changes are implemented with an internal soft-stepping algorithm that only changes the actual volume level by one 0.5-dB step every one or two ADC output samples, depending on the register programming (see page 0, registers 19 and 22). This soft-stepping ensures that volume control changes occur smoothly with no audible artifacts. On reset, the PGA gain defaults to a mute condition, and on power down, the PGA soft-steps the volume to mute before shutting down. A read-only flag is set whenever the gain applied by PGA equals the desired value set by the register. The soft-stepping control can also be disabled by programming a register bit. When soft stepping is enabled, the audio master clock must be applied to the part after the ADC power-down register is written to ensure the soft-stepping to mute has completed. When the ADC power-down flag is no longer set, the audio master clock can be shut down.

11.3.3.2.1 Stereo Audio ADC High-Pass Filter

Often in audio applications it is desirable to remove the dc offset from the converted audio data stream. The TLV320AIC3101 has a programmable first-order high-pass filter which can be used for this purpose. The digital filter coefficients are in 16-bit format and therefore use two 8-bit registers for each of the three coefficients, N0, N1, and D1. The transfer function of the digital high-pass filter is of the form:

Equation 1.

Programming the left channel is done by writing to page 1, registers 65–70, and the right channel is programmed by writing to page 1, registers 71–76. After the coefficients have been loaded, these ADC high-pass filter coefficients can be selected by writing to page 0, register 107, bits D7–D6, and the high-pass filter can be enabled by writing to page 0, register 12, bits D7–D4.

11.3.3.2.2 Automatic Gain Control (AGC)

An automatic gain control (AGC) circuit is included with the ADC and can be used to maintain nominally constant output signal amplitude when recording speech signals (it can be fully disabled if not desired). This circuitry automatically adjusts the PGA gain as the input signal becomes overly loud or very weak, such as when a person speaking into a microphone moves closer or farther from the microphone. The AGC algorithm has several programmable settings, including target gain, attack and decay time constants, noise threshold, and maximum PGA gain applicable that allow the algorithm to be fine-tuned for any particular application. The algorithm uses the absolute average of the signal (which is the average of the absolute value of the signal) as a measure of the nominal amplitude of the output signal.

Note that completely independent AGC circuitry is included with each ADC channel with entirely independent control over the algorithm from one channel to the next. This is attractive in cases where two microphones are used in a system, but may have different placement in the end equipment and require different dynamic performance for optimal system operation.

11.3.3.2.2.1 Target Level

The target level represents the nominal output level at which the AGC attempts to hold the ADC output signal level. The TLV320AIC3101 allows programming of eight different target levels, which can be programmed from –5.5 dB to –24 dB relative to a full-scale signal. Because the device reacts to the signal absolute average and not to peak levels, it is recommended that the target level be set with enough margin to avoid clipping at the occurrence of loud sounds.

11.3.3.2.2.2 Attack Time

The attack time determines how quickly the AGC circuitry reduces the PGA gain when the input signal is too loud. It can be varied from 7 ms to 1,408 ms. The extended right-channel attack time can be programmed by writing to page 0, register 103, and the left channel is programmed by writing to page 0, register 105.

11.3.3.2.2.3 Decay Time

The decay time determines how quickly the PGA gain is increased when the input signal is too low. It can be varied in the range from 0.05 s to 22.4 s. The extended right-channel decay time can be programmed by writing to page 0, register 104, and the left channel is programmed by writing to page 0, register 106.

The actual AGC decay time maximum is based on a counter length, so the maximum decay time scales with the clock setup that is used. Table 2 shows the relationship of the NCODEC ratio to the maximum time available for the AGC decay. In practice, these maximum times are extremely long for audio applications and should not limit any practical AGC decay time that is needed by the system.

Table 2. AGC Decay Time Restriction

NCODEC RATIO	MAXIMUM DECAY TIME (SECONDS)
1	4
1.5	5.6
2	8
2.5	9.6
3	11.2
3.5	11.2
4	16
4.5	16
5	19.2
5.5	22.4
6	22.4

11.3.3.2.2.4 Noise Gate Threshold

The noise gate threshold determines the level below which if the input speech average value falls, AGC considers it as a silence and hence brings down the gain to 0 dB in steps of 0.5 dB every sample period and sets the noise threshold flag. The gain stays at 0 dB unless the input speech signal average rises above the noise threshold setting. This ensures that noise does not get gained up in the absence of speech. Noise threshold level in the AGC algorithm is programmable from –30 dB to –90 dB relative to full scale. A disable noise gate feature is also available. This operation includes programmable debounce and hysteresis functionality to avoid the AGC gain from cycling between high gain and 0 dB when signals are near the noise threshold level. When the noise threshold flag is set, the status of gain applied by the AGC and the saturation flag should be ignored.

11.3.3.2.2.5 Maximum PGA Gain Applicable

The maximum PGA gain applicable allows the user to restrict the maximum PGA gain that can be applied by the AGC algorithm. This can be used for limiting PGA gain in situations where environmental noise is greater than programmed noise threshold. It can be programmed from 0 dB to 59.5 dB in steps of 0.5 dB.

Figure 18. Typical Operation of the AGC Algorithm During Speech Recording

Note that the time constants here are correct when the ADC is not in double-rate audio mode. The time constants are achieved using the f_S(ref) value programmed in the control registers. However, if the f_S(ref) is set in the registers to, for example, 48 kHz, but the actual audio clock or PLL programming actually results in a different f_S(ref) in practice, then the time constants would not be correct.

The actual AGC decay time maximum is based on a counter length, so the maximum decay time scales with the clock setup that is used. Table 2 shows the relationship of the NCODEC ratio to the maximum time available for the AGC decay. In practice, these maximum times are extremely long for audio applications and should not limit any practical AGC decay time that is needed by the system.

11.3.3.3 Stereo Audio DAC

The TLV320AIC3101 includes a stereo audio DAC supporting sampling rates from 8 kHz to 96 kHz. Each channel of the stereo audio DAC consists of a digital audio processing block, a digital interpolation filter, multibit digital delta-sigma modulator, and an analog reconstruction filter. The DAC is designed to provide enhanced performance at low sampling rates through increased oversampling and image filtering, thereby keeping quantization noise generated within the delta-sigma modulator and signal images strongly suppressed within the audio band to beyond 20 kHz. This is realized by keeping the upsampled rate constant at 128 f_S(ref) and changing the oversampling ratio as the input sample rate is changed. For an f_S(ref) of 48 kHz, the digital delta-sigma modulator always operates at a rate of 6.144 MHz. This ensures that quantization noise generated within the delta-sigma modulator stays low within the frequency band below 20 kHz at all sample rates. Similarly, for an f_S(ref) rate of 44.1 kHz, the digital delta-sigma modulator always operates at a rate of 5.6448 MHz.

The following restrictions apply in the case when the PLL is powered down and double-rate audio mode is enabled in the DAC.

Allowed Q values = 4, 8, 9, 12, 16

Q values where equivalent f_S(ref) can be achieved by turning on PLL

Q = 5, 6, 7 (set P = 5 / 6 / 7 and K = 16 and PLL enabled)

Q = 10, 14 (set P = 5, 7 and K = 8 and PLL enabled)

11.3.3.3.1 Digital Audio Processing for Playback

The DAC channel consists of optional filters for de-emphasis and bass, treble, midrange level adjustment, speaker equalization, and 3-D effects processing. The de-emphasis function is implemented by a programmable digital filter block with fully programmable coefficients (see page 1, registers 21–26 for the left channel and page 1, registers 47–52 for the right channel). If de-emphasis is not required in a particular application, this programmable filter block can be used for some other purpose. The de-emphasis filter transfer function is given by:

Equation 2.

where the N0, N1, and D1 coefficients are fully programmable individually for each channel. The coefficients that should be loaded to implement standard de-emphasis filters are given in Table 3.

Table 3. De-Emphasis Coefficients for Common Audio Sampling Rates

SAMPLING FREQUENCY	N0	N1	D1
32 kHz	16,950	–1,220	17,037
44.1 kHz	15,091	–2,877	20,555
48 kHz(1)	14,677	–3,283	21,374

(1) The 48-kHz coefficients listed in Table 3 are used as defaults.

In addition to the de-emphasis filter block, the DAC digital effects processing includes a fourth-order digital IIR filter with programmable coefficients (one set per channel). This filter is implemented as cascade of two biquad sections with frequency response given by:

Equation 3.

The N and D coefficients are fully programmable, and the entire filter can be enabled or bypassed. The structure of the filtering when configured for independent channel processing is shown in Figure 19, with LB1 corresponding to the first left-channel biquad filter using coefficients N0, N1, N2, D1, and D2. LB2 similarly corresponds to the second left-channel biquad filter using coefficients N3, N4, N5, D4, and D5. The RB1 and RB2 filters refer to the first and second right-channel biquad filters, respectively.

Figure 19. Structure of Digital Effects Processing for Independent Channel Processing

The coefficients for this filter implement a variety of sound effects, with bass boost or treble boost being the most commonly used in portable audio applications. The default N and D coefficients in the part are given in Table 4 and implement a shelving filter with 0-dB gain from dc to approximately 150 Hz, at which point it rolls off to a 3-dB attenuation for higher frequency signals, thus giving a 3-dB boost to signals below 150 Hz. The N and D coefficients are represented by 16-bit, 2s-complement numbers with values ranging from –32,768 to 32,767.

Table 4. Default Digital Effects Processing Filter Coefficients,
When in Independent Channel Processing Configuration

Coefficients
N0 = N3	D1 = D4	N1 = N4	D2 = D5	N2 = N5
27,619	32,131	–27,034	–31,506	26,461

The digital processing also includes capability to implement 3-D processing algorithms by providing means to process the mono mix of the stereo input, and then combine this with the individual channel signals for stereo output playback. The architecture of this processing mode, and the programmable filters available for use in the system, are shown in Figure 20. Note that the programmable attenuation block provides a method of adjusting the level of 3-D effect introduced into the final stereo output. This, combined with the fully programmable biquad filters in the system, enables the user to optimize the audio effects for a particular system and provide extensive differentiation from other systems using the same device.

Figure 20. Architecture of the Digital Audio Processing When 3-D Effects are Enabled

It is recommended that the digital effects filters should be disabled while the filter coefficients are being modified. While new coefficients are being written to the device over the control port, it is possible that a filter using partially updated coefficients may actually implement an unstable system and lead to oscillation or objectionable audio output. By disabling the filters, changing the coefficients, and then re-enabling the filters, these types of effects can be entirely avoided.

11.3.3.3.2 Digital Interpolation Filter

The digital interpolation filter upsamples the output of the digital audio processing block by the required oversampling ratio before data is provided to the digital delta-sigma modulator and analog reconstruction filter stages. The filter provides a linear phase output with a group delay of 21/f_S. In addition, programmable digital interpolation filtering is included to provide enhanced image filtering and reduce signal images caused by the upsampling process that are below 20 kHz. For example, upsampling an 8-kHz signal produces signal images at multiples of 8-kHz (i.e., 8 kHz, 16 kHz, 24 kHz, etc.). The images at 8 kHz and 16 kHz are below 20 kHz and still audible to the listener; therefore, they must be filtered heavily to maintain a good quality output. The interpolation filter is designed to maintain at least 65-dB rejection of images which are below 7.455 f_S. In order to use the programmable interpolation capability, f_S(ref) should be programmed to a higher rate (restricted to be in the range of 39 kHz to 53 kHz when the PLL is in use), and the actual f_S is set using the NCODEC divider, where NCODEC = NDAC = NADC. For example, if f_S = 8 kHz is required, then f_S(ref) can be set to 48 kHz, and the DAC f_S set to f_S(ref)/6. This ensures that all images of the 8-kHz data are sufficiently attenuated well beyond a 20-kHz audible frequency range.

Delta-Sigma Audio DAC

The stereo audio DAC incorporates a third-order multibit delta-sigma modulator followed by an analog reconstruction filter. The DAC provides high-resolution, low-noise performance, using oversampling and noise shaping techniques. The analog reconstruction filter design consists of a six-tap analog FIR filter followed by a continuous time RC filter. The analog FIR operates at a rate of 128 f_S(ref) (6.144 MHz when f_S(ref) = 48 kHz, 5.6448 MHz when f_S(ref) = 44.1 kHz). Note that the DAC analog performance may be degraded by excessive clock jitter on the MCLK input. Therefore, care must be taken to keep jitter on this clock to a minimum.

11.3.3.3.3 Audio DAC Digital Volume Control

The audio DAC includes a digital volume control block which implements a programmable digital gain. The volume level can be varied from 0 dB to –63.5 dB in 0.5-dB steps, in addition to a mute bit, independently for each channel. The volume level of both channels can also be changed simultaneously by the master volume control. Gain changes are implemented with a soft-stepping algorithm, which only changes the actual volume by one step per input sample, either up or down, until the desired volume is reached. The rate of soft-stepping can be slowed to one step per two input samples through a register bit.

Because of soft-stepping, the host does not know when the DAC has been actually muted. This may be important if the host wishes to mute the DAC before making a significant change, such as changing sample rates. In order to help with this situation, the device provides a flag back to the host via a read-only register bit that alerts the host when the part has completed the soft-stepping and the actual volume has reached the desired volume level. The soft-stepping feature can be disabled through register programming. If soft-stepping is enabled, the MCLK signal should be kept applied to the device until the DAC power-down flag is set. When this flag is set, the internal soft-stepping process and power-down sequence is complete, and the MCLK can then be stopped if desired.

The TLV320AIC3101 also includes functionality to detect when the user switches on or off the de-emphasis or digital audio processing functions, to first (1) soft-mute the DAC volume control, (2) change the operation of the digital effects processing, and (3) soft-unmute the part. This avoids any possible pop/clicks in the audio output due to instantaneous changes in the filtering. A similar algorithm is used when first powering up or powering down the DAC. The circuit begins operation at power up with the volume control muted, then soft-steps it up to the desired volume level. At power down, the logic first soft-steps the volume down to a mute level, then powers down the circuitry.

11.3.3.3.4 Increasing DAC Dynamic Range

The TLV320AIC3101 allows trading off dynamic range with power consumption. The DAC dynamic range can be increased by writing to page 0, register 109, bits D7–D6. The lowest DAC current setting is the default, and the dynamic range is displayed in the datasheet table. Increasing the current can increase the DAC dynamic range by up to 1.5 dB.

11.3.3.3.5 Analog Output Common-Mode Adjustment

The output common-mode voltage and output range of the analog output are determined by an internal band-gap reference, in contrast to other codecs that may use a divided version of the supply. This scheme is used to reduce the coupling of noise that may be on the supply (such as 217-Hz noise in a GSM cellphone) into the audio signal path.

However, due to the possible wide variation in analog supply range (2.7 V–3.6 V), an output common-mode voltage setting of 1.35 V, which would be used for a 2.7 V supply case, would be overly conservative if the supply is actually much larger, such as 3.3 V or 3.6 V. In order to optimize device operation, the TLV320AIC3101 includes a programmable output common-mode level, which can be set by register programming to a level most appropriate to the actual supply range used by a particular customer. The output common-mode level can be varied among four different values, ranging from 1.35 V (most appropriate for low supply ranges, near 2.7 V) to 1.8 V (most appropriate for high supply ranges, near 3.6 V). Note that there is also some limitation on the range of DVDD voltage as well in determining which setting is most appropriate.

Table 5. Appropriate Settings

CM SETTING	RECOMMENDED AVDD, DRVDD	RECOMMENDED DVDD
1.35	2.7 V–3.6 V	1.525 V–1.95 V
1.5	3 V–3.6 V	1.65 V–1.95 V
1.65 V	3.3 V–3.6 V	1.8 V–1.95 V
1.8 V	3.6 V	1.95 V

11.3.3.3.6 Audio DAC Power Control

The stereo DAC can be fully powered up or down, and in addition, the analog circuitry in each DAC channel can be powered up or down independently. This provides power savings when only a mono playback stream is needed.

11.3.4 Audio Analog Inputs

The TLV320AIC3101 includes six single-ended audio inputs. These pins connect through series resistors and switches to the virtual ground terminals of two fully differential operational amplifiers (one per ADC/PGA channel). By selecting to turn on only one set of switches per operational amplifier at a time, the inputs can be effectively muxed to each ADC PGA channel.

By selecting to turn on multiple sets of switches per operational amplifier at a time, mixing can also be achieved. Mixing of multiple inputs can easily lead to PGA outputs that exceed the range of the internal operational amplifiers, resulting in saturation and clipping of the mixed output signal. Whenever mixing is being implemented, the user should take adequate precautions to avoid such a saturation case from occurring. In general, the mixed signal should not exceed 2 Vp-p (single-ended).

In most mixing applications, there is also a general need to adjust the levels of the individual signals being mixed. For example, if a soft signal and a large signal are to be mixed and played together, the soft signal generally should be amplified to a level comparable to the large signal before mixing. In order to accommodate this need, the TLV320AIC3101 includes input level control on each of the individual inputs before they are mixed or muxed into the ADC PGAs, with gain programmable from 0 dB to –12 dB in 1.5-dB steps. Note that this input level control is not intended to be a volume control, but instead used occasionally for level setting. Soft-stepping of the input level control settings is implemented in this device, with the speed and functionality following the settings used by the ADC PGA for soft-stepping.

Figure 21 shows the single-ended mixing configuration for the left-channel ADC PGA, which enables mixing of the signals LINE1L, LINE2L, LINE1R, MIC3L, and MIC3R. The right-channel ADC PGA mix is similar, enabling mixing of the signals LINE1R, LINE2R, LINE1L, MIC3L, and MIC3R.

Figure 21. Left-Channel, Single-Ended Analog Input Mixing Configuration

11.3.5 Analog Fully Differential Line Output Drivers

The TLV320AIC3101 has two fully differential line output drivers, each capable of driving a 10-kΩ differential load. The output stage design leading to the fully differential line output drivers is shown in Figure 22 and Figure 23. This design includes extensive capability to adjust signal levels independently before any mixing occurs, beyond that already provided by the PGA gain and the DAC digital volume control.

Figure 22. Architecture of the Output Stage Leading to the Fully Differential Line Output Drivers

The PGA_L/R signals refer to the outputs of the ADC PGA stages that are similarly passed around the ADC to the output stage. Note that because both left- and right-channel signals are routed to all output drivers, a mono mix of any of the stereo signals can easily be obtained by setting the volume controls of both left- and right-channel signals to –6 dB and mixing them. Undesired signals can also be disconnected from the mix as well through register control.

Figure 23. Detail of the Volume Control and Mixing Function Shown in Figure 19 and Figure 31

The DAC_L/R signals are the outputs of the stereo audio DAC, which can be steered by register control based on the requirements of the system. If mixing of the DAC audio with other signals is not required, and the DAC output is only needed at the stereo line outputs, then it is recommended to use the routing through path DAC_L3/R3 to the fully differential stereo line outputs. This results not only in higher quality output performance, but also in lower-power operation, because the analog volume controls and mixing blocks ahead of these drivers can be powered down.

If instead the DAC analog output must be routed to multiple output drivers simultaneously (such as to LEFT_LOP/M and RIGHT_LOP/M) or must be mixed with other analog signals, then the DAC outputs should be switched through the DAC_L1/R1 path. This option provides the maximum flexibility for routing of the DAC analog signals to the output drivers

The TLV320AIC3101 includes an output level control on each output driver with limited gain adjustment from 0 dB to 9 dB. The output driver circuitry in this device are designed to provide a low distortion output while playing full-scale stereo DAC signals at a 0-dB gain setting. However, a higher amplitude output can be obtained at the cost of increased signal distortion at the output. This output level control allows the user to make this tradeoff based on the requirements of the end equipment. Note that this output level control is not intended to be used as a standard output volume control. It is expected to be used only sparingly for level setting, that is, adjustment of the fullscale output range of the device.

11.3.6 Analog High-Power Output Drivers

The TLV320AIC3101 includes four high-power output drivers with extensive flexibility in their usage. These output drivers are individually capable of driving 30 mW each into a 16-Ω load in single-ended configuration, and they can be used in pairs to drive up to 500 mW into an 8-Ω load connected in bridge-terminated load (BTL) configuration between two driver outputs.

The high-power output drivers can be configured in a variety of ways, including:

1. Driving up to two fully differential output signals
2. Driving up to four single-ended output signals
3. Driving two single-ended output signals, with one or two of the remaining drivers driving a fixed VCM level, for a pseudodifferential stereo output
4. Driving one or two 8-Ω speakers connected BTL between pairs of driver output pins
5. Driving stereo headphones in single-ended configuration with two drivers, while the remaining two drivers are connected in BTL configuration to an 8-Ω speaker

The output stage architecture leading to the high-power output drivers is shown in Figure 24, with the volume control and mixing blocks being effectively identical to that shown in Figure 23. Note that each of these drivers have a output level control block like those included with the line output drivers, allowing gain adjustment up to 9 dB on the output signal. As in the previous case, this output level adjustment is not intended to be used as a standard volume control, but instead is included for additional fullscale output signal level control.

Two of the output drivers, HPROUT and HPLOUT, include a direct connection path for the stereo DAC outputs to be passed directly to the output drivers and bypass the analog volume controls and mixing networks, using the DAC_L2/R2 path. As in the line output case, this functionality provides the highest quality DAC playback performance with reduced power dissipation, but can only be utilized if the DAC output does not need to route to multiple output drivers simultaneously, and if mixing of the DAC output with other analog signals is not needed.

Figure 24. Architecture of the Output Stage Leading to the High-Power Output Drivers

The high-power output drivers include additional circuitry to avoid artifacts on the audio output during power-on and power-off transient conditions. The user should first program the type of output configuration being used in page 0, register 14, to allow the device to select the optimal power-up scheme to avoid output artifacts. The power-up delay time for the high-power output drivers is also programmable over a wide range of time delays, from instantaneous up to 4 s, using page 0, register 42.

When these output drivers are powered down, they can be placed into a variety of output conditions based on register programming. If lowest-power operation is desired, then the outputs can be placed into a high-impedance state, and all power to the output stage is removed. However, this generally results in the output nodes drifting to rest near the upper or lower analog supply, due to small leakage currents at the pins. This then results in a longer delay requirement to avoid output artifacts during driver power on. In order to reduce this required power-on delay, the TLV320AIC3101 includes an option for the output pins of the drivers to be weakly driven to the VCM level they would normally rest at when powered with no signal applied. This output VCM level is determined by an internal band-gap voltage reference, and thus results in extra power dissipation when the drivers are in power down. However, this option provides the fastest method for transitioning the drivers from power down to full-power operation without any output artifact introduced.

The device includes a further option that falls between the other two—although it requires less power drawn while the output drivers are in power down, it also takes a slightly longer delay to power up without artifact than if the band-gap reference is kept alive. In this alternate mode, the powered-down output driver pin is weakly driven to a voltage of approximately half the DRVDD1/2 supply level using an internal voltage divider. This voltage does not match the actual VCM of a fully powered driver, but due to the output voltage being close to its final value, a much shorter power-up delay time setting can be used and still avoid any audible output artifacts. These output voltage options are controlled in page 0, register 42.

The high-power output drivers can also be programmed to power up first with the output level (gain) control in a highly attenuated state; then the output driver automatically reduces the output attenuation slowly to reach the programmed output gain. This capability is enabled by default but can be enabled in page 0, register40.

11.3.7 Input Impedance and VCM Control

The TLV320AIC3101 includes several programmable settings to control analog input pins, particularly when they are not selected for connection to an ADC PGA. The default option allows unselected inputs to be put into a high-impedance state, such that the input impedance seen looking into the device is extremely high. Note, however, that the pins on the device do include protection diode circuits connected to AVDD and AVSS. Thus, if any voltage is driven onto a pin approximately one diode drop (~0.6 V) above AVDD or one diode drop below AVSS, these protection diodes begin conducting current, resulting in an effective impedance that no longer appears as a high-impedance state.

Another programmable option for unselected analog inputs is to weakly hold them at the common-mode input voltage of the ADC PGA (which is determined by an internal band-gap voltage reference). This is useful to keep the ac-coupling capacitors connected to analog inputs biased up at a normal dc level, thus avoiding the need for them to charge up suddenly when the input is changed from being unselected to selected for connection to an ADC PGA. This option is controlled in page 0, registers 20 and 23. The user should ensure this option is disabled when an input is selected for connection to an ADC PGA or selected for the analog input bypass path, because it can corrupt the recorded input signal if left operational when an input is selected.

In most cases, the analog input pins on the TLV320AIC3101 should be ac-coupled to analog input sources, the only exception to this generally being if an ADC is being used for dc voltage measurement. The ac-coupling capacitor causes a high-pass filter pole to be inserted into the analog signal path, so the size of the capacitor must be chosen to move that filter pole sufficiently low in frequency to cause minimal effect on the processed analog signal. The input impedance of the analog inputs when selected for connection to an ADC PGA varies with the setting of the input level control, starting at approximately 20 kΩ with an input level control setting of 0 dB, and increasing to approximately 80 kΩ when the input level control is set at –12 dB. For example, using a 0.1-μF ac-coupling capacitor at an analog input results in a high-pass filter pole of 80 Hz when the 0-dB input level control setting is selected.

11.3.8 MICBIAS Generation

The TLV320AIC3101 includes a programmable microphone bias output voltage (MICBIAS), capable of providing output voltages of 2 V or 2.5 V (both derived from the on-chip band-gap voltage) with 4-mA output current drive. In addition, the MICBIAS may be programmed to be switched to AVDD directly through an on-chip switch, or it can be powered down completely when not needed, for power savings. This function is controlled by register programming in page 0, register 25.

11.3.9 Short-Circuit Output Protection

The TLV320AIC3101 includes programmable short-circuit protection for the high-power output drivers, for maximum flexibility in a given application. By default, if these output drivers are shorted, they automatically limit the maximum amount of current that can be sourced to or sunk from a load, thereby protecting the device from an overcurrent condition. In this mode, the user can read page 0, register 95 to determine whether the part is in short-circuit protection or not, and then decide whether to program the device to power down the output drivers. However, the device includes further capability to power down an output driver automatically whenever it goes into short-circuit protection, without requiring intervention from the user. In this case, the output driver stays in a power-down condition until the user specifically programs it to power down and then power back up again, to clear the short-circuit flag.

11.3.10 Jack/Headset Detection

The TLV320AIC3101 includes extensive capability to monitor a headphone, microphone, or headset jack, determine if a plug has been inserted into the jack, and then determine what type of headset/headphone is wired to the plug. Figure 25 shows one configuration of the device that enables detection and determination of headset type when a pseudo-differential (capless) stereo headphone output configuration is used. The registers used for this function are page 0, registers 14, 96, 97, and 13. The type of headset detected can be read back from page 0, register 13. Note that for best results, it is recommended to select a MICBIAS value as high as possible, and to program the output driver common-mode level at a 1.35-V or 1.5-V level.

Figure 25. Configuration of Device for Jack Detection Using a Pseudo-Differential (Capless) Headphone Output Connection

A modified output configuration used when the output drivers are ac-coupled is shown in Figure 26. Note that in this mode, the device cannot accurately determine if the inserted headphone is a mono or stereo headphone.

Figure 26. Configuration of Device for Jack Detection Using an AC-Coupled Stereo Headphone Output Connection

An output configuration for the case of the outputs driving fully differential stereo headphones is shown in Figure 27. In this mode, there is a requirement on the jack side that either HPLCOM or HPLOUT get shorted to ground if the plug is removed, which can be implemented using a spring terminal in a jack. For this mode to function properly, short-circuit detection should be enabled and configured to power down the drivers if a short-circuit is detected. The registers that control this functionality are in page 0, register 38, bits D2–D1.

Figure 27. Configuration of Device for Jack Detection Using a Fully Differential Stereo Headphone Output Connection

11.4.1 Bypass Path Mode

The TLV320AIC3101 is a versatile device designed for low-power applications. In some cases, only a few features of the device are required. For these applications, the unused stages of the device must be powered down to save power and an alternate route should be used. This is called a bypass path. The bypass path modes let the device to save power by turning off unused stages, like ADC, DAC and PGA.

11.4.1.3 Passive Analog Bypass During Power Down

Programming the TLV320AIC3101 to passive analog bypass occurs by configuring the output stage switches for passthrough. This is done by opening switches SW-L0, SW-L3, SW-R0, and SW-R3 and closing either SW-L1 or SW-L2 and SW-R1 or SW-R2. See Figure 28. Programming this mode is done by writing to page 0, register 108.

Connecting the MIC1LP/LINE1LP input signal to the LEFT_LOP pin is done by closing SW-L1 and opening SW-L0; this action is done by writing a 1 to page 0, register 108, bit D0. Connecting the MIC2LP/LINE2LP input signal to the LEFT_LOP pin is done by closing SW-L2 and opening SW-L0; this action is done by writing a 1 to page 0, register 108, bit D2. Connecting the MIC1LM/LINE1LM input signal to the LEFT_LOM pin is done by closing SW-L4 and opening SW-L3; this action is done by writing a 1 to page 0, register 108, bit D1.

Connecting the MIC1RP/LINE1RP input signal to the RIGHT_LOP pin is done by closing SW-R1 and opening SW-R0; this action is done by writing a 1 to page 0, register 108, bit D4. Connecting the MIC2RP/LINE2RP input signal to the RIGHT_LOP pin is done by closing SW-R2 and opening SW-R0; this action is done by writing a 1 to page 0, register 108, bit D6. Connecting MIC1RM/LINE1RM input signal to the RIGHT_LOM pin is done by closing SW-R4 and opening SW-R3; this action is done by writing a 1 to page 0, register 108, bit D5. A diagram of the passive analog bypass mode configuration is shown in Figure 28.

In general, connecting two switches to the same output pin should be avoided, as this error shorts two input signals together, and would likely cause distortion of the signal as the two signals are in contention. Poor frequency response would also likely occur.

Figure 28. Passive Analog Bypass Mode Configuration

11.4.2 Digital Audio Processing for Record Path

In applications where record-only is selected, and DAC is powered down, the playback path signal processing blocks can be used in the ADC record path. These filtering blocks can support high-pass, low-pass, band-pass or notch filtering. In this mode, the record-only path has switches SW-D1 through SW-D4 closed, and reroutes the ADC output data through the digital signal processing blocks. Because the DAC digital signal processing blocks are being re-used, naturally the addresses of these digital filter coefficients are the same as for the DAC digital processing and are located on page 1, registers 1–52. This record-only mode is enabled by powering down both DACs by writing to page 0, register 37, bits D7–D6 (D7 = D6 = 0). Next, enable the digital filter pathway for the ADC by writing a 1 to page 0, register 107, bit D3. (Note, this pathway is only enabled if both DACs are powered down.) This record-only path can be seen in Figure 29.

Figure 29. Record-Only Mode With Digital Processing Path Enabled

11.5.1 I²C Control Interface

The TLV320AIC3101 supports the I²C control protocol using 7-bit addressing and is capable of both standard and fast modes. For I²C fast mode, note that the minimum timing for each of t_HD-STA, t_SU-STA, and t_SU-STO is 0.9 μs, as seen in Figure 30. The TLV320AIC3101 responds to the I²C address of 001 1000. I²C is a two-wire, open-drain interface supporting multiple devices and masters on a single bus. Devices on the I²C bus only drive the bus lines LOW by connecting them to ground; they never drive the bus lines HIGH. Instead, the bus wires are pulled HIGH by pullup resistors, so the bus wires are HIGH when no device is driving them LOW. This way, two devices cannot conflict; if two devices drive the bus simultaneously, there is no driver contention.

Figure 30. I²C Interface Timing

Communication on the I²C bus always takes place between two devices, one acting as the master and the other acting as the slave. Both masters and slaves can read and write, but slaves can only do so under the direction of the master. Some I²C devices can act as masters or slaves, but the TLV320AIC3101 can only act as a slave device.

An I²C bus consists of two lines, SDA and SCL. SDA carries data; SCL provides the clock. All data is transmitted across the I²C bus in groups of eight bits. To send a bit on the I²C bus, the SDA line is driven to the appropriate level while SCL is LOW (a LOW on SDA indicates the bit is zero; a HIGH indicates the bit is one). Once the SDA line has settled, the SCL line is brought HIGH, then LOW. This pulse on SCL clocks the SDA bit into the receiver shift register.

The I²C bus is bidirectional: the SDA line is used both for transmitting and receiving data. When a master reads from a slave, the slave drives the data line; when a master sends to a slave, the master drives the data line. Under normal circumstances the master drives the clock line.

Most of the time the bus is idle, no communication is taking place, and both lines are HIGH. When communication is taking place, the bus is active. Only master devices can start a communication. They do this by causing a START condition on the bus. Normally, the data line is only allowed to change state while the clock line is LOW. If the data line changes state while the clock line is HIGH, it is either a START condition or its counterpart, a STOP condition. A START condition is when the clock line is HIGH and the data line goes from HIGH to LOW. A STOP condition is when the clock line is HIGH and the data line goes from LOW to HIGH.

After the master issues a START condition, it sends a byte that indicates which slave device it wants to communicate with. This byte is called the address byte. Each device on an I²C bus has a unique 7-bit address to which it responds. (Slaves can also have 10-bit addresses; see the I²C specification for details.) The master sends an address in the address byte, together with a bit that indicates whether it wishes to read from or write to the slave device.

Every byte transmitted on the I²C bus, whether it is address or data, is acknowledged with an acknowledge bit. When a master has finished sending a byte (eight data bits) to a slave, it stops driving SDA and waits for the slave to acknowledge the byte. The slave acknowledges the byte by pulling SDA LOW. The master then sends a clock pulse to clock the acknowledge bit. Similarly, when a master has finished reading a byte, it pulls SDA LOW to acknowledge this to the slave. It then sends a clock pulse to clock the bit.

A not-acknowledge is performed by simply leaving SDA HIGH during an acknowledge cycle. If a device is not present on the bus, and the master attempts to address it, it receives a not-acknowledge because no device is present at that address to pull the line LOW.

When a master has finished communicating with a slave, it may issue a STOP condition. When a STOP condition is issued, the bus becomes idle again. A master may also issue another START condition. When a START condition is issued while the bus is active, it is called a repeated START condition.

The TLV320AIC3101 also responds to and acknowledges a general call, which consists of the master issuing a command with a slave-address byte of 00h.

Figure 31. I²C Write

Figure 32. I²C Read

In the case of an I²C register write, if the master does not issue a STOP condition, then the device enters auto-increment mode. So in the next eight clocks, the data on SDA is treated as data for the next incremental register.

Similarly, in the case of an I²C register read, after the device has sent out the 8-bit data from the addressed register, if the master issues an acknowledge, the slave takes over control of SDA bus and transmit for the next 8 clocks the data of the next incremental register.

11.5.2 I²C Bus Debug in a Glitched System

Occasionally, some systems may encounter noise or glitches on the I²C bus. In the unlikely event that this affects bus performance, then it can be useful to use the I²C Debug register. This feature terminates the I²C bus error allowing this I²C device and system to resume communications. The I²C bus error detector is enabled by default. The TLV320AIC3101 I²C error detector status can be read from page 0, register 107, bit D0. If desired, the detector can be disabled by writing to page 0, register 107, bit D2.

Table 6. Page 0/Register 0: Page Select Register

Table 7. Page 0/Register 1: Software Reset Register

Table 8. Page 0/Register 2: Codec Sample Rate Select Register

Table 9. Page 0/Register 3: PLL Programming Register A

Table 10. Page 0/Register 4: PLL Programming Register B

Table 11. Page 0/Register 5: PLL Programming Register C⁽¹⁾

Table 12. Page 0/Register 6: PLL Programming Register D

Table 13. Page 0/Register 7: Codec Data-Path Setup Register

Table 14. Page 0/Register 8: Audio Serial Data Interface Control Register A

Table 15. Page 0/Register 9: Audio Serial Data Interface Control Register B

Table 16. Page 0/Register 10: Audio Serial Data Interface Control Register C

Table 17. Page 0/Register 11: Audio Codec Overflow Flag Register

Table 18. Page 0/Register 12: Audio Codec Digital Filter Control Register

Table 19. Page 0/Register 13: Reserved

Table 20. Page 0/Register 14: Headset/Button Press Detection Register B

Table 21. Page 0/Register 15: Left-ADC PGA Gain Control Register

Table 22. Page 0/Register 16: Right-ADC PGA Gain Control Register

Table 23. Page 0/Register 17: MIC2L/R to Left-ADC Control Register

Table 24. Page 0/Register 18: MIC2/LINE2 to Right-ADC Control Register

Table 25. Page 0/Register 19: MIC1LP/LINE1LP to Left-ADC Control Register

Table 26. Page 0/Register 20: Left Channel Analog Inputs to CM Connection Register

Table 27. Page 0/Register 21: MIC1RP/LINE1RP to Left-ADC Control Register

Table 28. Page 0/Register 22: MIC1RP/LINE1RP to Right-ADC Control Register

Table 29. Page 0/Register 23: Right Channel Analog Inputs to CM Connection Register

Table 30. Page 0/Register 24: MIC1LP/LINE1LP to Right-ADC Control Register

Table 31. Page 0/Register 25: MICBIAS Control Register

Table 32. Page 0/Register 26: Left-AGC Control Register A

Table 33. Page 0/Register 27: Left-AGC Control Register B

Table 34. Page 0/Register 28: Left-AGC Control Register C

Table 35. Page 0/Register 29: Right-AGC Control Register A

Table 36. Page 0/Register 30: Right-AGC Control Register B

Table 37. Page 0/Register 31: Right-AGC Control Register C

Table 38. Page 0/Register 32: Left-AGC Gain Register

Table 39. Page 0/Register 33: Right-AGC Gain Register

Table 40. Page 0/Register 34: Left-AGC Noise Gate Debounce Register

Table 41. Page 0/Register 35: Right-AGC Noise Gate Debounce Register

Table 42. Page 0/Register 36: ADC Flag Register

Table 43. Page 0/Register 37: DAC Power and Output Driver Control Register

Table 44. Page 0/Register 38: High-Power Output Driver Control Register

Table 45. Page 0/Register 39: Reserved Register

Table 46. Page 0/Register 40: High-Power Output Stage Control Register

Table 47. Page 0/Register 41: DAC Output Switching Control Register

Table 48. Page 0/Register 42: Output Driver Pop Reduction Register

Table 49. Page 0/Register 43: Left-DAC Digital Volume Control Register

Table 50. Page 0/Register 44: Right-DAC Digital Volume Control Register

Table 51. Output Stage Volume Control Settings and Gains

Table 52. Page 0/Register 45: Reserved Register

Table 53. Page 0/Register 46: PGA_L to HPLOUT Volume Control Register

Table 54. Page 0/Register 47: DAC_L1 to HPLOUT Volume Control Register

Table 55. Page 0/Register 48: Reserved Register

Table 56. Page 0/Register 49: PGA_R to HPLOUT Volume Control Register

Table 57. Page 0/Register 50: DAC_R1 to HPLOUT Volume Control Register

Table 58. Page 0/Register 51: HPLOUT Output Level Control Register

Table 59. Page 0/Register 52: Reserved Register

Table 60. Page 0/Register 53: PGA_L to HPLCOM Volume Control Register

Table 61. Page 0/Register 54: DAC_L1 to HPLCOM Volume Control Register

Table 62. Page 0/Register 55: Reserved Register

Table 63. Page 0/Register 56: PGA_R to HPLCOM Volume Control Register

Table 64. Page 0/Register 57: DAC_R1 to HPLCOM Volume Control Register

Table 65. Page 0/Register 58: HPLCOM Output Level Control Register

Table 66. Page 0/Register 59: Reserved Register

Table 67. Page 0/Register 60: PGA_L to HPROUT Volume Control Register

Table 68. Page 0/Register 61: DAC_L1 to HPROUT Volume Control Register

Table 69. Page 0/Register 62: Reserved Register

Table 70. Page 0/Register 63: PGA_R to HPROUT Volume Control Register

Table 71. Page 0/Register 64: DAC_R1 to HPROUT Volume Control Register

Table 72. Page 0/Register 65: HPROUT Output Level Control Register

Table 73. Page 0/Register 66: Reserved Register

Table 74. Page 0/Register 67: PGA_L to HPRCOM Volume Control Register

Table 75. Page 0/Register 68: DAC_L1 to HPRCOM Volume Control Register

Table 76. Page 0/Register 69: Reserved Register

Table 77. Page 0/Register 70: PGA_R to HPRCOM Volume Control Register

Table 78. Page 0/Register 71: DAC_R1 to HPRCOM Volume Control Register

Table 79. Page 0/Register 72: HPRCOM Output Level Control Register

Table 80. Page 0/Registers 73–78: Reserved

Table 81. Page 0/Register 79: Reserved

Table 82. Page 0/Register 80: Reserved

Table 83. Page 0/Register 81: PGA_L to LEFT_LOP/M Volume Control Register

Table 84. Page 0/Register 82: DAC_L1 to LEFT_LOP/M Volume Control Register

Table 85. Page 0/Register 83: Reserved Register

Table 86. Page 0/Register 84: PGA_R to LEFT_LOP/M Volume Control Register

Table 87. Page 0/Register 85: DAC_R1 to LEFT_LOP/M Volume Control Register

Table 88. Page 0/Register 86: LEFT_LOP/M Output Level Control Register

Table 89. Page 0/Register 87: Reserved Register

Table 90. Page 0/Register 88: PGA_L to RIGHT_LOP/M Volume Control Register

Table 91. Page 0/Register 89: DAC_L1 to RIGHT_LOP/M Volume Control Register

Table 92. Page 0/Register 90: Reserved Register

Table 93. Page 0/Register 91: PGA_R to RIGHT_LOP/M Volume Control Register

Table 94. Page 0/Register 92: DAC_R1 to RIGHT_LOP/M Volume Control Register

Table 95. Page 0/Register 93: RIGHT_LOP/M Output Level Control Register

Table 96. Page 0/Register 94: Module Power Status Register

Table 97. Page 0/Register 95: Output Driver Short-Circuit Detection Status Register

Table 98. Page 0/Register 96: Sticky Interrupt Flags Register

Table 99. Page 0/Register 97: Real-Time Interrupt Flags Register

Table 100. Page 0/Register 98–100: Reserved Registers

Table 101. Page 0/Register 101: Clock Register

Table 102. Page 0/Register 102: Clock Generation Control Register

Table 103. Page 0/Register 103: Left-AGC New Programmable Attack Time Register

Table 104. Page 0/Register 104: Left-AGC New Programmable Decay Time Register⁽¹⁾

Table 105. Page 0/Register 105: Right-AGC New Programmable Attack Time Register

Table 106. Page 0/Register 106: Right-AGC New Programmable Decay Time Register⁽¹⁾

Table 107. Page 0/Register 107: New Programmable ADC Digital Path and I²C Bus Condition Register

Table 108. Page 0/Register 108: Passive Analog Signal Bypass Selection During Power Down Register⁽¹⁾

Table 109. Page 0/Register 109: DAC Quiescent Current Adjustment Register

Table 110. Page 0/Register 110–127: Reserved Registers

Table 111. Page 1/Register 0: Page Select Register

Table 112. Page 1/Register 1: Left-Channel Audio Effects Filter N0 Coefficient MSB Register⁽¹⁾

Table 113. Page 1/Register 2: Left-Channel Audio Effects Filter N0 Coefficient LSB Register

Table 114. Page 1/Register 3: Left-Channel Audio Effects Filter N1 Coefficient MSB Register

Table 115. Page 1/Register 4: Left-Channel Audio Effects Filter N1 Coefficient LSB Register

Table 116. Page 1/Register 5: Left-Channel Audio Effects Filter N2 Coefficient MSB Register

Table 117. Page 1/Register 6: Left-Channel Audio Effects Filter N2 Coefficient LSB

Table 118. Page 1/Register 7: Left-Channel Audio Effects Filter N3 Coefficient MSB Register

Table 119. Page 1/Register 8: Left-Channel Audio Effects Filter N3 Coefficient LSB Register

Table 120. Page 1/Register 9: Left-Channel Audio Effects Filter N4 Coefficient MSB Register

Table 121. Page 1/Register 10: Left-Channel Audio Effects Filter N4 Coefficient LSB Register

Table 122. Page 1/Register 11: Left-Channel Audio Effects Filter N5 Coefficient MSB Register

Table 123. Page 1/Register 12: Left-Channel Audio Effects Filter N5 Coefficient LSB Register

Table 124. Page 1/Register 13: Left-Channel Audio Effects Filter D1 Coefficient MSB Register

Table 125. Page 1/Register 14: Left-Channel Audio Effects Filter D1 Coefficient LSB Register

Table 126. Page 1/Register 15: Left-Channel Audio Effects Filter D2 Coefficient MSB Register

Table 127. Page 1/Register 16: Left-Channel Audio Effects Filter D2 Coefficient LSB Register

Table 128. Page 1/Register 17: Left-Channel Audio Effects Filter D4 Coefficient MSB Register

Table 129. Page 1/Register 18: Left-Channel Audio Effects Filter D4 Coefficient LSB Register

Table 130. Page 1/Register 19: Left-Channel Audio Effects Filter D5 Coefficient MSB Register

Table 131. Page 1/Register 20: Left-Channel Audio Effects Filter D5 Coefficient LSB Register

Table 132. Page 1/Register 21: Left-Channel De-Emphasis Filter N0 Coefficient MSB Register

Table 133. Page 1/Register 22: Left-Channel De-Emphasis Filter N0 Coefficient LSB Register

Table 134. Page 1/Register 23: Left-Channel De-Emphasis Filter N1 Coefficient MSB Register

Table 135. Page 1/Register 24: Left-Channel De-Emphasis Filter N1 Coefficient LSB Register

Table 136. Page 1/Register 25: Left-Channel De-Emphasis Filter D1 Coefficient MSB Register

Table 137. Page 1/Register 26: Left-Channel De-Emphasis Filter D1 Coefficient LSB Register

Table 138. Page 1/Register 27: Right-Channel Audio Effects Filter N0 Coefficient MSB Register

Table 139. Page 1/Register 28: Right-Channel Audio Effects Filter N0 Coefficient LSB Register

Table 140. Page 1/Register 29: Right-Channel Audio Effects Filter N1 Coefficient MSB Register

Table 141. Page 1/Register 30: Right-Channel Audio Effects Filter N1 Coefficient LSB Register

Table 142. Page 1/Register 31: Right-Channel Audio Effects Filter N2 Coefficient MSB Register

Table 143. Page 1/Register 32: Right-Channel Audio Effects Filter N2 Coefficient LSB Register

Table 144. Page 1/Register 33: Right-Channel Audio Effects Filter N3 Coefficient MSB Register

Table 145. Page 1/Register 34: Right-Channel Audio Effects Filter N3 Coefficient LSB Register

Table 146. Page 1/Register 35: Right-Channel Audio Effects Filter N4 Coefficient MSB Register

Table 147. Page 1/Register 36: Right-Channel Audio Effects Filter N4 Coefficient LSB Register

Table 148. Page 1/Register 37: Right-Channel Audio Effects Filter N5 Coefficient MSB Register

Table 149. Page 1/Register 38: Right-Channel Audio Effects Filter N5 Coefficient LSB Register

Table 150. Page 1/Register 39: Right-Channel Audio Effects Filter D1 Coefficient MSB Register

Table 151. Page 1/Register 40: Right-Channel Audio Effects Filter D1 Coefficient LSB Register

Table 152. Page 1/Register 41: Right-Channel Audio Effects Filter D2 Coefficient MSB Register

Table 153. Page 1/Register 42: Right-Channel Audio Effects Filter D2 Coefficient LSB Register

Table 154. Page 1/Register 43: Right-Channel Audio Effects Filter D4 Coefficient MSB Register

Table 155. Page 1/Register 44: Right-Channel Audio Effects Filter D4 Coefficient LSB Register

Table 156. Page 1/Register 45: Right-Channel Audio Effects Filter D5 Coefficient MSB Register

Table 157. Page 1/Register 46: Right-Channel Audio Effects Filter D5 Coefficient LSB Register

Table 158. Page 1/Register 47: Right-Channel De-Emphasis Filter N0 Coefficient MSB Register

Table 159. Page 1/Register 48: Right-Channel De-Emphasis Filter N0 Coefficient LSB Register

Table 160. Page 1/Register 49: Right-Channel De-Emphasis Filter N1 Coefficient MSB Register

Table 161. Page 1/Register 50: Right-Channel De-Emphasis Filter N1 Coefficient LSB Register

Table 162. Page 1/Register 51: Right-Channel De-Emphasis Filter D1 Coefficient MSB Register

Table 163. Page 1/Register 52: Right-Channel De-Emphasis Filter D1 Coefficient LSB Register

Table 164. Page 1/Register 53: 3-D Attenuation Coefficient MSB Register

Table 165. Page 1/Register 54: 3-D Attenuation Coefficient LSB Register

Table 166. Page 1/Register 55–64: Reserved Registers

Table 167. Page 1/Register 65: Left-Channel ADC High-Pass Filter N0 Coefficient MSB Register

Table 168. Page 1/Register 66: Left-Channel ADC High-Pass Filter N0 Coefficient LSB Register

Table 169. Page 1/Register 67: Left-Channel ADC High-Pass Filter N1 Coefficient MSB Register

Table 170. Page 1/Register 68: Left-Channel ADC High-Pass Filter N1 Coefficient LSB Register

Table 171. Page 1/Register 69: Left-Channel ADC High-Pass Filter D1 Coefficient MSB Register

Table 172. Page 1/Register 70: Left-Channel ADC High-Pass Filter D1 Coefficient LSB Register

Table 173. Page 1/Register 71: Right-Channel ADC High-Pass Filter N0 Coefficient MSB Register

Table 174. Page 1/Register 72: Right-Channel ADC High-Pass Filter N0 Coefficient LSB Register

Table 175. Page 1/Register 73: Right-Channel ADC High-Pass Filter N1 Coefficient MSB Register

Table 176. Page 1/Register 74: Right-Channel ADC High-Pass Filter N1 Coefficient LSB Register

Table 177. Page 1/Register 75: Right-Channel ADC High-Pass Filter D1 Coefficient MSB Register

Table 178. Page 1/Register 76: Right-Channel ADC High-Pass Filter D1 Coefficient LSB Register

Table 179. Page 1/Registers 77–127: Reserved Registers