SLAS715C June   2010  – January 2023 TLV320AIC3104-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Device Comparison
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information
    5. 8.5  Electrical Characteristics
    6. 8.6  Switching Characteristics I2S/LJF/RJF Timing in Master Mode
    7. 8.7  Switching Characteristics I2S/LJF/RJF Timing in Slave Mode
    8. 8.8  Switching Characteristics DSP Timing in Master Mode
    9. 8.9  Switching Characteristics DSP Timing in Slave Mode
    10. 8.10 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Audio Data Converters
      2. 9.3.2  Stereo Audio ADC
        1. 9.3.2.1 Stereo Audio ADC High-Pass Filter
      3. 9.3.3  Automatic Gain Control (AGC)
      4. 9.3.4  Stereo Audio DAC
      5. 9.3.5  Digital Audio Processing for Playback
      6. 9.3.6  Digital Interpolation Filter
      7. 9.3.7  Delta-Sigma Audio DAC
      8. 9.3.8  Audio DAC Digital Volume Control
      9. 9.3.9  Analog Output Common-mode Adjustment
      10. 9.3.10 Audio DAC Power Control
      11. 9.3.11 Audio Analog Inputs
      12. 9.3.12 Analog Input Bypass Path Functionality
      13. 9.3.13 ADC PGA Signal Bypass Path Functionality
      14. 9.3.14 Input Impedance and VCM Control
      15. 9.3.15 MICBIAS Generation
      16. 9.3.16 Analog Fully Differential Line Output Drivers
      17. 9.3.17 Analog High-Power Output Drivers
      18. 9.3.18 Short-Circuit Output Protection
      19. 9.3.19 Jack and Headset Detection
    4. 9.4 Device Functional Modes
      1. 9.4.1 Digital Audio Processing for Record Path
      2. 9.4.2 Increasing DAC Dynamic Range
      3. 9.4.3 Passive Analog Bypass During Power Down
      4. 9.4.4 Hardware Reset
    5. 9.5 Programming
      1. 9.5.1  Digital Control Serial Interface
      2. 9.5.2  I2C Control Interface
      3. 9.5.3  I2C Bus Debug in a Glitched System
      4. 9.5.4  Digital Audio Data Serial Interface
      5. 9.5.5  Right-Justified Mode
      6. 9.5.6  Left-Justified Mode
      7. 9.5.7  I2S Mode
      8. 9.5.8  DSP Mode
      9. 9.5.9  TDM Data Transfer
      10. 9.5.10 Audio Clock Generation
    6. 9.6 Register Maps
      1. 9.6.1 Output Stage Volume Controls
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 External Speaker Driver in Infotainment and Cluster Applications
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curves
      2. 10.2.2 External Speaker Amplifier With Separate Line Outputs
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Device Nomenclature
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Community Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.5.4 Digital Audio Data Serial Interface

Audio data is transferred between the host processor and the TLV320AIC3104-Q1 via the digital audio data serial interface. The audio bus of the TLV320AIC3104-Q1 can be configured for left- or right-justified, I 2S, DSP, or TDM modes of operation, where communication with standard audio interfaces is supported within the TDM mode. These modes are all MSB-first, with data width programmable as 16, 20, 24, or 32 bits. In addition, the word clock (WCLK) and bit clock (BCLK) can be independently configured in either master or slave mode, for flexible connectivity to a wide variety of processors.

The word clock (WCLK) is used to define the beginning of a frame, and can be programmed as either a pulse or a square-wave signal. The frequency of this clock corresponds to the selected ADC and DAC sampling frequency.

The bit clock (BCLK) is used to clock in and out the digital audio data across the serial bus. When in master mode, this signal can be programmed in two further modes: continuous transfer mode, and 256-clock mode. In continuous transfer mode, only the minimal number of bit clocks required to transfer the audio data are generated, so in general the number of bit clocks per frame is two times the data width. For example, if the data width is chosen as 16 bits, then 32-bit clocks are generated per frame. If the bit clock signal in master mode is to be used by a PLL in another device, then the 16-bit or 32-bit data-width selections are recommended be used. These cases result in a low-jitter bit clock signal being generated, with frequencies of 32 fS or 64 fS. For a 20-bit and 24-bit data width in master mode, the bit clocks generated in each frame are not all of equal period because the device does not have a clean 40-fS or 48-fS clock signal readily available. The average frequency of the bit clock signal is still accurate in these cases (40 fS or 48 fS), but the resulting clock signal has higher jitter than in the 16-bit and 32-bit cases.

In 256-clock mode, a constant 256 bit clocks per frame are generated, independent of the data width chosen. The TLV320AIC3104-Q1 further includes programmability to place the DOUT line in the high-impedance state during all bit clocks when valid data are not being sent. By combining this capability with the ability to program at what bit clock in a frame the audio data begins, time-division multiplexing (TDM) can be accomplished, resulting in multiple codecs able to use a single audio serial data bus.

When the digital audio data serial interface is powered down when configured in master mode, the pins associated with the interface are put into a high-impedance state.