SLAS715D June   2010  – October 2024 TLV320AIC3104-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Switching Characteristics I2S/LJF/RJF Timing in Master Mode
    7. 6.7  Switching Characteristics I2S/LJF/RJF Timing in Slave Mode
    8. 6.8  Switching Characteristics DSP Timing in Master Mode
    9. 6.9  Switching Characteristics DSP Timing in Slave Mode
    10. 6.10 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Audio Data Converters
      2. 7.3.2  Stereo Audio ADC
        1. 7.3.2.1 Stereo Audio ADC High-Pass Filter
      3. 7.3.3  Automatic Gain Control (AGC)
      4. 7.3.4  Stereo Audio DAC
      5. 7.3.5  Digital Audio Processing for Playback
      6. 7.3.6  Digital Interpolation Filter
      7. 7.3.7  Delta-Sigma Audio DAC
      8. 7.3.8  Audio DAC Digital Volume Control
      9. 7.3.9  Analog Output Common-mode Adjustment
      10. 7.3.10 Audio DAC Power Control
      11. 7.3.11 Audio Analog Inputs
      12. 7.3.12 Analog Input Bypass Path Functionality
      13. 7.3.13 ADC PGA Signal Bypass Path Functionality
      14. 7.3.14 Input Impedance and VCM Control
      15. 7.3.15 MICBIAS Generation
      16. 7.3.16 Analog Fully Differential Line Output Drivers
      17. 7.3.17 Analog High-Power Output Drivers
      18. 7.3.18 Short-Circuit Output Protection
      19. 7.3.19 Jack and Headset Detection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Digital Audio Processing for Record Path
      2. 7.4.2 Increasing DAC Dynamic Range
      3. 7.4.3 Passive Analog Bypass During Power Down
      4. 7.4.4 Hardware Reset
    5. 7.5 Programming
      1. 7.5.1  Digital Control Serial Interface
      2. 7.5.2  I2C Control Interface
      3. 7.5.3  I2C Bus Debug in a Glitched System
      4. 7.5.4  Digital Audio Data Serial Interface
      5. 7.5.5  Right-Justified Mode
      6. 7.5.6  Left-Justified Mode
      7. 7.5.7  I2S Mode
      8. 7.5.8  DSP Mode
      9. 7.5.9  TDM Data Transfer
      10. 7.5.10 Audio Clock Generation
  9. 8 Register Maps
    1. 8.1 Output Stage Volume Controls
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 External Speaker Driver in Infotainment and Cluster Applications
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 External Speaker Amplifier With Separate Line Outputs
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Device Nomenclature
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Community Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.1 Output Stage Volume Controls

A basic analog volume control with range from 0 dB to –78 dB and mute is replicated multiple times in the output stage network, connected to each of the analog signals that route to the output stage. In addition, to enable completely independent mixing operations to be performed for each output driver, each analog signal coming into the output stage may have up to seven separate volume controls. These volume controls all have approximately 0.5-dB step programmability over most of the gain range, with steps increasing slightly at the lowest attenuations. Table 8-46 lists the detailed gain versus programmed setting for this basic volume control.

Table 8-46 Output Stage Volume Control Settings and Gains
Gain Setting Analog Gain
(dB)		 Gain Setting Analog Gain
(dB)		 Gain Setting Analog Gain
(dB)		 Gain Setting Analog Gain
(dB)
 0  0   30 –15   60 –30.1  90 –45.2
 1 –0.5 31 –15.5 61 –30.6  91 –45.8
 2 –1   32 –16   62 –31.1  92 –46.2
 3 –1.5 33 –16.5 63 –31.6  93 –46.7
 4 –2   34 –17   64 –32.1  94 –47.4
 5 –2.5 35 –17.5 65 –32.6  95 –47.9
 6 –3   36 –18   66 –33.1  96 –48.2
 7 –3.5 37 –18.6 67 –33.6  97 –48.7
 8 –4   38 –19.1 68 –34.1  98 –49.3
 9 –4.5 39 –19.6 69 –34.6  99 –50  
10 –5   40 –20.1 70 –35.1 100 –50.3
11 –5.5 41 –20.6 71 –35.7 101 –51  
12 –6   42 –21.1 72 –36.1 102 –51.4
13 –6.5 43 –21.6 73 –36.7 103 –51.8
14 –7   44 –22.1 74 –37.1 104 –52.2
15 –7.5 45 –22.6 75 –37.7 105 –52.7
16 –8   46 –23.1 76 –38.2 106 –53.7
17 –8.5 47 –23.6 77 –38.7 107 –54.2
18 –9   48 –24.1 78 –39.2 108 –55.3
19 –9.5 49 –24.6 79 –39.7 109 –56.7
20 –10   50 –25.1 80 –40.2 110 –58.3
21 –10.5 51 –25.6 81 –40.7 111 –60.2
22 –11   52 –26.1 82 –41.2 112 –62.7
23 –11.5 53 –26.6 83 –41.7 113 –64.3
24 –12   54 –27.1 84 –42.2 114 –66.2
25 –12.5 55 –27.6 85 –42.7 115 –68.7
26 –13   56 –28.1 86 –43.2 116 –72.2
27 –13.5 57 –28.6 87 –43.8 117 –78.3
28 –14   58 –29.1 88 –44.3 118–127 Mute
29 –14.5 59 –29.6 89 –44.8
Table 8-47 Page 0, Register 45: Reserved Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W 0000 0000 Reserved. Do not write to this register.
Table 8-48 Page 0, Register 46: PGA_L to HPLOUT Volume Control Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7 R/W 0 PGA_L Output Routing Control
0: PGA_L is not routed to HPLOUT
1: PGA_L is routed to HPLOUT
D6–D0 R/W 000 0000 PGA_L to HPLOUT Analog Volume Control
For 7-bit register settings versus analog gain values, see Table 8-46.
Table 8-49 Page 0, Register 47: DAC_L1 to HPLOUT Volume Control Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7 R/W 0 DAC_L1 Output Routing Control
0: DAC_L1 is not routed to HPLOUT.
1: DAC_L1 is routed to HPLOUT.
D6–D0 R/W 000 0000 DAC_L1 to HPLOUT Analog Volume Control
For 7-bit register settings versus analog gain values, see Table 8-46.
Table 8-50 Page 0, Register 48: Reserved Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W 0000 0000 Reserved. Do not write to this register.
Table 8-51 Page 0, Register 49: PGA_R to HPLOUT Volume Control Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7 R/W 0 PGA_R Output Routing Control
0: PGA_R is not routed to HPLOUT
1: PGA_R is routed to HPLOUT
D6–D0 R/W 000 0000 PGA_R to HPLOUT Analog Volume Control
For 7-bit register settings versus analog gain values, see Table 8-46.
Table 8-52 Page 0, Register 50: DAC_R1 to HPLOUT Volume Control Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7 R/W 0 DAC_R1 Output Routing Control
0: DAC_R1 is not routed to HPLOUT.
1: DAC_R1 is routed to HPLOUT.
D6–D0 R/W 000 0000 DAC_R1 to HPLOUT Analog Volume Control
For 7-bit register settings versus analog gain values, see Table 8-46.
Table 8-53 Page 0, Register 51: HPLOUT Output Level Control Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D4 R/W 0000 HPLOUT Output Level Control
0000: Output level control = 0 dB
0001: Output level control = 1 dB
0010: Output level control = 2 dB
...
1000: Output level control = 8 dB
1001: Output level control = 9 dB
1010–1111: Reserved. Do not write these sequences to these register bits.
D3 R/W 0 HPLOUT Mute
0: HPLOUT is muted.
1: HPLOUT is not muted.
D2 R/W 1 HPLOUT Power-Down Drive Control
0: HPLOUT is weakly driven to a common-mode when powered down.
1: HPLOUT is high-impedance when powered down.
D1 R 0 HPLOUT Volume Control Status
0: Not all programmed gains to HPLOUT have been applied yet.
1: All programmed gains to HPLOUT have been applied.
D0 R/W 0 HPLOUT Power Control
0: HPLOUT is not fully powered up.
1: HPLOUT is fully powered up.
Table 8-54 Page 0, Register 52: Reserved Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W 0000 0000 Reserved. Do not write to this register.
Table 8-55 Page 0, Register 53: PGA_L to HPLCOM Volume Control Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7 R/W 0 PGA_L Output Routing Control
0: PGA_L is not routed to HPLCOM.
1: PGA_L is routed to HPLCOM.
D6–D0 R/W 000 0000 PGA_L to HPLCOM Analog Volume Control
For 7-bit register settings versus analog gain values, see Table 8-46.
Table 8-56 Page 0, Register 54: DAC_L1 to HPLCOM Volume Control Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7 R/W 0 DAC_L1 Output Routing Control
0: DAC_L1 is not routed to HPLCOM.
1: DAC_L1 is routed to HPLCOM.
D6–D0 R/W 000 0000 DAC_L1 to HPLCOM Analog Volume Control
For 7-bit register settings versus analog gain values, see Table 8-46.
Table 8-57 Page 0, Register 55: Reserved Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W 0000 0000 Reserved. Do not write to this register.
Table 8-58 Page 0, Register 56: PGA_R to HPLCOM Volume Control Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7 R/W 0 PGA_R Output Routing Control
0: PGA_R is not routed to HPLCOM.
1: PGA_R is routed to HPLCOM.
D6–D0 R/W 000 0000 PGA_R to HPLCOM Analog Volume Control
For 7-bit register settings versus analog gain values, see Table 8-46.
Table 8-59 Page 0, Register 57: DAC_R1 to HPLCOM Volume Control Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7 R/W 0 DAC_R1 Output Routing Control
0: DAC_R1 is not routed to HPLCOM.
1: DAC_R1 is routed to HPLCOM.
D6–D0 R/W 000 0000 DAC_R1 to HPLCOM Analog Volume Control
For 7-bit register settings versus analog gain values, see Table 8-46.
Table 8-60 Page 0, Register 58: HPLCOM Output Level Control Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D4 R/W 0000 HPLCOM Output Level Control
0000: Output level control = 0 dB
0001: Output level control = 1 dB
0010: Output level control = 2 dB
...
1000: Output level control = 8 dB
1001: Output level control = 9 dB
1010–1111: Reserved. Do not write these sequences to these register bits.
D3 R/W 0 HPLCOM Mute
0: HPLCOM is muted.
1: HPLCOM is not muted.
D2 R/W 1 HPLCOM Power-Down Drive Control
0: HPLCOM is weakly driven to a common mode when powered down.
1: HPLCOM is high-impedance when powered down.
D1 R 1 HPLCOM Volume Control Status
0: Not all programmed gains to HPLCOM have been applied yet.
1: All programmed gains to HPLCOM have been applied.
D0 R/W 0 HPLCOM Power Control
0: HPLCOM is not fully powered up.
1: HPLCOM is fully powered up.
Table 8-61 Page 0, Register 59: Reserved Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W 0000 0000 Reserved. Do not write to this register.
Table 8-62 Page 0, Register 60: PGA_L to HPROUT Volume Control Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7 R/W 0 PGA_L Output Routing Control
0: PGA_L is not routed to HPROUT.
1: PGA_L is routed to HPROUT.
D6–D0 R/W 000 0000 PGA_L to HPROUT Analog Volume Control
For 7-bit register settings versus analog gain values, see Table 8-46.
Table 8-63 Page 0, Register 61: DAC_L1 to HPROUT Volume Control Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7 R/W 0 DAC_L1 Output Routing Control
0: DAC_L1 is not routed to HPROUT.
1: DAC_L1 is routed to HPROUT.
D6–D0 R/W 000 0000 DAC_L1 to HPROUT Analog Volume Control
For 7-bit register settings versus analog gain values, see Table 8-46.
Table 8-64 Page 0, Register 62: Reserved Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W 0000 0000 Reserved. Do not write to this register.
Table 8-65 Page 0, Register 63: PGA_R to HPROUT Volume Control Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7 R/W 0 PGA_R Output Routing Control
0: PGA_R is not routed to HPROUT.
1: PGA_R is routed to HPROUT.
D6–D0 R/W 000 0000 PGA_R to HPROUT Analog Volume Control
For 7-bit register settings versus analog gain values, see Table 8-46.
Table 8-66 Page 0, Register 64: DAC_R1 to HPROUT Volume Control Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7 R/W 0 DAC_R1 Output Routing Control
0: DAC_R1 is not routed to HPROUT.
1: DAC_R1 is routed to HPROUT.
D6–D0 R/W 000 0000 DAC_R1 to HPROUT Analog Volume Control
For 7-bit register settings versus analog gain values, see Table 8-46.
Table 8-67 Page 0, Register 65: HPROUT Output Level Control Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D4 R/W 0000 HPROUT Output Level Control
0000: Output level control = 0 dB
0001: Output level control = 1 dB
0010: Output level control = 2 dB
...
1000: Output level control = 8 dB
1001: Output level control = 9 dB
1010–1111: Reserved. Do not write these sequences to these register bits.
D3 R/W 0 HPROUT Mute
0: HPROUT is muted.
1: HPROUT is not muted.
D2 R/W 1 HPROUT Power-Down Drive Control
0: HPROUT is weakly driven to a common mode when powered down.
1: HPROUT is high-impedance when powered down.
D1 R 1 HPROUT Volume Control Status
0: Not all programmed gains to HPROUT have been applied yet.
1: All programmed gains to HPROUT have been applied.
D0 R/W 0 HPROUT Power Control
0: HPROUT is not fully powered up.
1: HPROUT is fully powered up.
Table 8-68 Page 0, Register 66: Reserved Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W 0000 0000 Reserved. Do not write to this register.
Table 8-69 Page 0, Register 67: PGA_L to HPRCOM Volume Control Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7 R/W 0 PGA_L Output Routing Control
0: PGA_L is not routed to HPRCOM.
1: PGA_L is routed to HPRCOM.
D6–D0 R/W 000 0000 PGA_L to HPRCOM Analog Volume Control
For 7-bit register settings versus analog gain values, see Table 8-46.
Table 8-70 Page 0, Register 68: DAC_L1 to HPRCOM Volume Control Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7 R/W 0 DAC_L1 Output Routing Control
0: DAC_L1 is not routed to HPRCOM.
1: DAC_L1 is routed to HPRCOM.
D6–D0 R/W 000 0000 DAC_L1 to HPRCOM Analog Volume Control
For 7-bit register settings versus analog gain values, see Table 8-46.
Table 8-71 Page 0, Register 69: Reserved Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W 0000 0000 Reserved. Do not write to this register.
Table 8-72 Page 0, Register 70: PGA_R to HPRCOM Volume Control Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7 R/W 0 PGA_R Output Routing Control
0: PGA_R is not routed to HPRCOM.
1: PGA_R is routed to HPRCOM.
D6–D0 R/W 000 0000 PGA_R to HPRCOM Analog Volume Control
For 7-bit register settings versus analog gain values, see Table 8-46.
Table 8-73 Page 0, Register 71: DAC_R1 to HPRCOM Volume Control Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7 R/W 0 DAC_R1 Output Routing Control
0: DAC_R1 is not routed to HPRCOM.
1: DAC_R1 is routed to HPRCOM.
D6–D0 R/W 000 0000 DAC_R1 to HPRCOM Analog Volume Control
For 7-bit register settings versus analog gain values, see Table 8-46.
Table 8-74 Page 0, Register 72: HPRCOM Output Level Control Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D4 R/W 0000 HPRCOM Output Level Control
0000: Output level control = 0 dB
0001: Output level control = 1 dB
0010: Output level control = 2 dB
...
1000: Output level control = 8 dB
1001: Output level control = 9 dB
1010–1111: Reserved. Do not write these sequences to these register bits.
D3 R/W 0 HPRCOM Mute
0: HPRCOM is muted.
1: HPRCOM is not muted.
D2 R/W 1 HPRCOM Power-Down Drive Control
0: HPRCOM is weakly driven to a common mode when powered down.
1: HPRCOM is high-impedance when powered down.
D1 R 1 HPRCOM Volume Control Status
0: Not all programmed gains to HPRCOM have been applied yet.
1: All programmed gains to HPRCOM have been applied.
D0 R/W 0 HPRCOM Power Control
0: HPRCOM is not fully powered up.
1: HPRCOM is fully powered up.
Table 8-75 Page 0, Registers 73–78: Reserved
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R 0000 0000 Reserved. Do not write to these registers.
Table 8-76 Page 0, Register 79: Reserved
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R 0000 0010 Reserved. Do not write to this register.
Table 8-77 Page 0, Register 80: Reserved
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R 0000 0000 Reserved. Do not write to this register.
Table 8-78 Page 0, Register 81: PGA_L to LEFT_LOP/M Volume Control Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7 R/W 0 PGA_L Output Routing Control
0: PGA_L is not routed to LEFT_LOP/M.
1: PGA_L is routed to LEFT_LOP/M.
D6–D0 R/W 000 0000 PGA_L to LEFT_LOP/M Analog Volume Control
For 7-bit register settings versus analog gain values, see Table 8-46.
Table 8-79 Page 0, Register 82: DAC_L1 to LEFT_LOP/M Volume Control Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7 R/W 0 DAC_L1 Output Routing Control
0: DAC_L1 is not routed to LEFT_LOP/M.
1: DAC_L1 is routed to LEFT_LOP/M.
D6–D0 R/W 000 0000 DAC_L1 to LEFT_LOP/M Analog Volume Control
For 7-bit register settings versus analog gain values, see Table 8-46.
Table 8-80 Page 0, Register 83: Reserved Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W 0000 0000 Reserved. Do not write to this register.
Table 8-81 Page 0, Register 84: PGA_R to LEFT_LOP/M Volume Control Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7 R/W 0 PGA_R Output Routing Control
0: PGA_R is not routed to LEFT_LOP/M.
1: PGA_R is routed to LEFT_LOP/M.
D6–D0 R/W 000 0000 PGA_R to LEFT_LOP/M Analog Volume Control
For 7-bit register settings versus analog gain values, see Table 8-46.
Table 8-82 Page 0, Register 85: DAC_R1 to LEFT_LOP/M Volume Control Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7 R/W 0 DAC_R1 Output Routing Control
0: DAC_R1 is not routed to LEFT_LOP/M.
1: DAC_R1 is routed to LEFT_LOP/M.
D6–D0 R/W 000 0000 DAC_R1 to LEFT_LOP/M Analog Volume Control
For 7-bit register settings versus analog gain values, see Table 8-46.
Table 8-83 Page 0, Register 86: LEFT_LOP/M Output Level Control Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D4 R/W 0000 LEFT_LOP/M Output Level Control
0000: Output level control = 0 dB
0001: Output level control = 1 dB
0010: Output level control = 2 dB
...
1000: Output level control = 8 dB
1001: Output level control = 9 dB
1010–1111: Reserved. Do not write these sequences to these register bits.
D3 R/W 0 LEFT_LOP/M Mute
0: LEFT_LOP/M is muted.
1: LEFT_LOP/M is not muted.
D2 R 0 Reserved. Do not write to this register bit.
D1 R 1 LEFT_LOP/M Volume Control Status
0: Not all programmed gains to LEFT_LOP/M have been applied yet.
1: All programmed gains to LEFT_LOP/M have been applied.
D0 R/W 0 LEFT_LOP/M Power Status
0: LEFT_LOP/M is not fully powered up.
1: LEFT_LOP/M is fully powered up.
Table 8-84 Page 0, Register 87: Reserved Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W 0000 0000 Reserved. Do not write to this register.
Table 8-85 Page 0, Register 88: PGA_L to RIGHT_LOP/M Volume Control Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7 R/W 0 PGA_L Output Routing Control
0: PGA_L is not routed to RIGHT_LOP/M.
1: PGA_L is routed to RIGHT_LOP/M.
D6–D0 R/W 000 0000 PGA_L to RIGHT_LOP/M Analog Volume Control
For 7-bit register settings versus analog gain values, see Table 8-46.
Table 8-86 Page 0, Register 89: DAC_L1 to RIGHT_LOP/M Volume Control Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7 R/W 0 DAC_L1 Output Routing Control
0: DAC_L1 is not routed to RIGHT_LOP/M.
1: DAC_L1 is routed to RIGHT_LOP/M.
D6–D0 R/W 000 0000 DAC_L1 to RIGHT_LOP/M Analog Volume Control
For 7-bit register settings versus analog gain values, see Table 8-46.
Table 8-87 Page 0, Register 90: Reserved Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W 0000 0000 Reserved. Do not write to this register.
Table 8-88 Page 0, Register 91: PGA_R to RIGHT_LOP/M Volume Control Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7 R/W 0 PGA_R Output Routing Control
0: PGA_R is not routed to RIGHT_LOP/M.
1: PGA_R is routed to RIGHT_LOP/M.
D6–D0 R/W 000 0000 PGA_R to RIGHT_LOP/M Analog Volume Control
For 7-bit register settings versus analog gain values, see Table 8-46.
Table 8-89 Page 0, Register 92: DAC_R1 to RIGHT_LOP/M Volume Control Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7 R/W 0 DAC_R1 Output Routing Control
0: DAC_R1 is not routed to RIGHT_LOP/M.
1: DAC_R1 is routed to RIGHT_LOP/M.
D6–D0 R/W 000 0000 DAC_R1 to RIGHT_LOP/M Analog Volume Control
For 7-bit register settings versus analog gain values, see Table 8-46.
Table 8-90 Page 0, Register 93: RIGHT_LOP/M Output Level Control Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D4 R/W 0000 RIGHT_LOP/M Output Level Control
0000: Output level control = 0 dB
0001: Output level control = 1 dB
0010: Output level control = 2 dB
...
1000: Output level control = 8 dB
1001: Output level control = 9 dB
1010–1111: Reserved. Do not write these sequences to these bits.
D3 R/W 0 RIGHT_LOP/M Mute
0: RIGHT_LOP/M is muted.
1: RIGHT_LOP/M is not muted.
D2 R 0 Reserved. Do not write to this register bit.
D1 R 1 RIGHT_LOP/M Volume Control Status
0: All programmed gains to RIGHT_LOP/M have been applied.
1: Not all programmed gains to RIGHT_LOP/M have been applied yet
D0 R/W 0 RIGHT_LOP/M Power Status
0: RIGHT_LOP/M is not fully powered up.
1: RIGHT_LOP/M is fully powered up.
Table 8-91 Page 0, Register 94: Module Power Status Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7 R 0 Left-DAC Power Status
0: Left DAC is not fully powered up.
1: Left DAC is fully powered up.
D6 R 0 Right-DAC Power Status
0: Right DAC is not fully powered up.
1: Right DAC is fully powered up.
D5 R 0 Reserved. Write only 0 to this bit.
D4 R 0 LEFT_LOP/M Power Status
0: LEFT_LOP/M output driver is powered down.
1: LEFT_LOP/M output driver is powered up.
D3 R 0 RIGHT_LOP/M Power Status
0: RIGHT_LOP/M is not fully powered up.
1: RIGHT_LOP/M is fully powered up.
D2 R 0 HPLOUT Driver Power Status
0: HPLOUT Driver is not fully powered up.
1: HPLOUT Driver is fully powered up.
D1 R 0 HPROUT Driver Power Status
0: HPROUT Driver is not fully powered up.
1: HPROUT Driver is fully powered up.
D0 R 0 Reserved. Do not write to this bit.
Table 8-92 Page 0, Register 95: Output Driver Short-Circuit Detection Status Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7 R 0 HPLOUT Short-Circuit Detection Status
0: No short circuit detected at HPLOUT
1: Short circuit detected at HPLOUT
D6 R 0 HPROUT Short-Circuit Detection Status
0: No short circuit detected at HPROUT
1: Short circuit detected at HPROUT
D5 R 0 HPLCOM Short-Circuit Detection Status
0: No short circuit detected at HPLCOM
1: Short circuit detected at HPLCOM
D4 R 0 HPRCOM Short-Circuit Detection Status
0: No short circuit detected at HPRCOM
1: Short circuit detected at HPRCOM
D3 R 0 HPLCOM Power Status
0: HPLCOM is not fully powered up.
1: HPLCOM is fully powered up.
D2 R 0 HPRCOM Power Status
0: HPRCOM is not fully powered up.
1: HPRCOM is fully powered up.
D1–D0 R 00 Reserved. Do not write to these bits.
Table 8-93 Page 0, Register 96: Sticky Interrupt Flags Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7 R 0 HPLOUT Short-Circuit Detection Status
0: No short circuit detected at HPLOUT driver
1: Short circuit detected at HPLOUT driver
D6 R 0 HPROUT Short-Circuit Detection Status
0: No short circuit detected at HPROUT driver
1: Short circuit detected at HPROUT driver
D5 R 0 HPLCOM Short-Circuit Detection Status
0: No short circuit detected at HPLCOM driver
1: Short circuit detected at HPLCOM driver
D4 R 0 HPRCOM Short-Circuit Detection Status
0: No short circuit detected at HPRCOM driver
1: Short circuit detected at HPRCOM driver
D3 R 0 Reserved. Do not write to this bit.
D2 R 0 Headset Detection Status
0: No headset insertion/removal is detected.
1: Headset insertion/removal is detected.
D1 R 0 Left ADC AGC Noise Gate Status
0: Left ADC signal power is greater than or equal to noise threshold for left AGC.
1: Left ADC signal power is less than noise threshold for left AGC.
D0 R/W 0 Right ADC AGC Noise Gate Status
0: Right ADC signal power is greater than or equal to noise threshold for right AGC.
1: Right ADC signal power is less than noise threshold for right AGC.
Table 8-94 Page 0, Register 97: Real-Time Interrupt Flags Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7 R 0 HPLOUT Short-Circuit Detection Status
0: No short circuit detected at HPLOUT driver
1: Short circuit detected at HPLOUT driver
D6 R 0 HPROUT Short-Circuit Detection Status
0: No short circuit detected at HPROUT driver
1: Short circuit detected at HPROUT driver
D5 R 0 HPLCOM Short-Circuit Detection Status
0: No short circuit detected at HPLCOM driver
1: Short circuit detected at HPLCOM driver
D4 R 0 HPRCOM Short-Circuit Detection Status
0: No short circuit detected at HPRCOM driver
1: Short circuit detected at HPRCOM driver
D3 R 0 Reserved. Do not write to this bit.
D2 R 0 Headset Detection Status
0: No headset insertion/removal is detected.
1: Headset insertion/removal is detected.
D1 R 0 Left ADC AGC Noise Gate Status
0: Left ADC signal power is greater than noise threshold for left AGC.
1: Left ADC signal power lower than noise threshold for left AGC.
D0 R 0 Right ADC AGC Noise Gate Status
0: Right ADC signal power is greater than noise threshold for right AGC.
1: Right ADC signal power is lower than noise threshold for right AGC.
Table 8-95 Page 0, Register 98–100: Reserved Registers
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R 0000 0000 Reserved. Do not write to these registers.
Table 8-96 Page 0, Register 101: Clock Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D1 R 0000 000 Reserved. Write only zeros to these bits.((1))
D0 R/W 0 CODEC_CLKIN Source Selection
0: CODEC_CLKIN uses PLLDIV_OUT
1: CODEC_CLKIN uses CLKDIV_OUT
(1) Bits D7–D1 in register 101 are only valid in I2C control mode, when SELECT = 0.
Table 8-97 Page 0, Register 102: Clock Generation Control Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D6 R/W 00 CLKDIV_IN Source Selection
00: CLKDIV_IN uses MCLK.
01: CLKDIV_IN uses GPIO2.
10: CLKDIV_IN uses BCLK.
11: Reserved. Do not use.
D5–D4 R/W 00 PLLCLK_IN Source Selection
00: PLLCLK_IN uses MCLK.
01: PLLCLK_IN uses GPIO2.
10: PLLCLK _IN uses BCLK.
11: Reserved. Do not use.
D3–D0 R/W 0010 Reserved. Write only 0010 to these bits.
Table 8-98 Page 0, Register 103: Left-AGC New Programmable Attack Time Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7 R/W 0 Attack Time Register Selection
0: Attack time for the left AGC is generated from page 0, register 26.
1: Attack time for the left AGC is generated from this register.
D6–D5 R/W 00 Baseline AGC Attack time
00: Left-AGC attack time = 7 ms
01: Left-AGC attack time = 8 ms
10: Left-AGC attack time = 10 ms
11: Left-AGC attack time = 11 ms
D4–D2 R/W 000 Multiplication Factor for Baseline AGC
000: Multiplication factor for the baseline AGC attack time = 1
001: Multiplication factor for the baseline AGC attack time = 2
010: Multiplication factor for the baseline AGC attack time = 4
011: Multiplication factor for the baseline AGC attack time = 8
100: Multiplication factor for the baseline AGC attack time = 16
101: Multiplication factor for the baseline AGC attack time = 32
110: Multiplication factor for the baseline AGC attack time = 64
111: Multiplication factor for the baseline AGC attack time = 128
D1–D0 R/W 00 Reserved. Write only zeros to these bits.
Table 8-99 Page 0, Register 104: Left-AGC New Programmable Decay Time Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7 R/W 0 Decay Time Register Selection (1)
0: Decay time for the left AGC is generated from page 0, register 26.
1: Decay time for the left AGC is generated from this register.
D6–D5 R/W 00 Baseline AGC Decay Time
00: Left-AGC decay time = 50 ms
01: Left-AGC decay time = 150 ms
10: Left-AGC decay time = 250 ms
11: Left-AGC decay time = 350 ms
D4–D2 R/W 000 Multiplication Factor for Baseline AGC
000: Multiplication factor for the baseline AGC decay time = 1
001: Multiplication factor for the baseline AGC decay time = 2
010: Multiplication factor for the baseline AGC decay time = 4
011: Multiplication factor for the baseline AGC decay time = 8
100: Multiplication factor for the baseline AGC decay time = 16
101: Multiplication factor for the baseline AGC decay time = 32
110: Multiplication factor for the baseline AGC decay time = 64
111: Multiplication factor for the baseline AGC decay time = 128
D1–D0 R/W 00 Reserved. Write only zeros to these bits.
(1) Decay time is limited based on NCODEC ratio that is selected. For
NCODEC = 1, Maximum decay time = 4 s
NCODEC = 1.5, Maximum decay time = 5.6 s
NCODEC = 2, Maximum decay time = 8 s
NCODEC = 2.5, Maximum decay time = 9.6 s
NCODEC = 3 or 3.5, Maximum decay time = 11.2 s
NCODEC = 4 or 4.5, Maximum decay time = 16 s
NCODEC = 5, Maximum decay time = 19.2 s
NCODEC = 5.5 or 6, Maximum decay time = 22.4 s
Table 8-100 Page 0, Register 105: Right-AGC New Programmable Attack Time Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7 R/W 0 Attack Time Register Selection
0: Attack time for the right AGC is generated from page 0, register 29.
1: Attack time for the right AGC is generated from this register.
D6–D5 R/W 00 Baseline AGC attack time
00: Right-AGC attack time = 7 ms
01: Right-AGC attack time = 8 ms
10: Right-AGC attack time = 10 ms
11: Right-AGC attack time = 11 ms
D4–D2 R/W 000 Multiplication Factor for Baseline AGC
000: Multiplication factor for the baseline AGC attack time = 1
001: Multiplication factor for the baseline AGC attack time = 2
010: Multiplication factor for the baseline AGC attack time = 4
011: Multiplication factor for the baseline AGC attack time = 8
100: Multiplication factor for the baseline AGC attack time = 16
101: Multiplication factor for the baseline AGC attack time = 32
110: Multiplication factor for the baseline AGC attack time = 64
111: Multiplication factor for the baseline AGC attack time = 128
D1–D0 R/W 00 Reserved. Write only zeros to these bits.
Table 8-101 Page 0, Register 106: Right-AGC New Programmable Decay Time Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7 R/W 0 Decay Time Register Selection(1)
0: Decay time for the right AGC is generated from page 0, register 29.
1: Decay time for the right AGC is generated from this register.
D6–D5 R/W 00 Baseline AGC Decay Time
00: Right-AGC decay time = 50 ms
01: Right-AGC decay time = 150 ms
10: Right-AGC decay time = 250 ms
11: Right-AGC decay time = 350 ms
D4–D2 R/W 000 Multiplication Factor for Baseline AGC
000: Multiplication factor for the baseline AGC decay time = 1
001: Multiplication factor for the baseline AGC decay time = 2
010: Multiplication factor for the baseline AGC decay time = 4
011: Multiplication factor for the baseline AGC decay time = 8
100: Multiplication factor for the baseline AGC decay time = 16
101: Multiplication factor for the baseline AGC decay time = 32
110: Multiplication factor for the baseline AGC decay time = 64
111: Multiplication factor for the baseline AGC decay time = 128
D1–D0 R/W 00 Reserved. Write only zeros to these bits.
(1) Decay time is limited based on NCODEC ratio that is selected. For
NCODEC = 1, Maximum decay time = 4 seconds
NCODEC = 1.5, Maximum decay time = 5.6 seconds
NCODEC = 2, Maximum decay time = 8 seconds
NCODEC = 2.5, Maximum decay time = 9.6 seconds
NCODEC = 3 or 3.5, Maximum decay time = 11.2 seconds
NCODEC = 4 or 4.5, Maximum decay time = 16 seconds
NCODEC = 5, Maximum decay time = 19.2 seconds
NCODEC = 5.5 or 6, Maximum decay time = 22.4 seconds
Table 8-102 Page 0, Register 107: New Programmable ADC Digital Path and I2C Bus Condition Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7 R/W 0 Left-Channel High-Pass Filter Coefficient Selection
0: Default coefficients are used when ADC high pass is enabled.
1: Programmable coefficients are used when ADC high pass is enabled.
D6 R/W 0 Right-Channel High-Pass Filter Coefficient Selection
0: Default coefficients are used when ADC high pass is enabled.
1: Programmable coefficients are used when ADC high pass is enabled.
D5–D4 R/W 00 ADC Decimation Filter Configuration
00: Left and right digital microphones are used.
01: Left digital microphone and right analog microphone are used.
10: Left analog microphone and right digital microphone are used.
11: Left and right analog microphones are used.
D3 R/W 0 ADC Digital Output to Programmable Filter Path Selection
0: No additional programmable filters other than the HPF are used for the ADC.
1: The programmable filter is connected to ADC output, if both DACs are powered down.
D2 R/W 0 I2C Bus Condition Detector
0: Internal logic is enabled to detect an I2C bus error, and clears the bus error condition.
1: Internal logic is disabled to detect an I2C bus error.
D1 R 0 Reserved. Write only zero to these register bits.
D0 R 0 I2C Bus Error Detection Status
0: I2C bus error is not detected.
1: I2C bus error is detected. This bit is cleared by reading this register.
Table 8-103 Page 0, Register 108: Passive Analog Signal Bypass Selection During Power Down Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7 R/W 0 Reserved. Write only zero to this bit.
D6 R/W 0 Reserved. Write only zero to these register bits.
D5 R/W 0 LINE1RM Path Selection
0: Normal signal path
1: Signal is routed by a switch to RIGHT_LOM.
D4 R/W 0 LINE1RP Path Selection
0: Normal signal path
1: Signal is routed by a switch to RIGHT_LOP.
D3 R/W 0 Reserved. Write only zero to this bit.
D2 R/W 0 Reserved. Write only zero to these register bits.
D1 R/W 0 LINE1LM Path Selection
0: Normal signal path
1: Signal is routed by a switch to LEFT_LOM.
D0 R/W 0 LINE1LP Path Selection
0: Normal signal path
1: Signal is routed by a switch to LEFT_LOP.

Based on the register 108 settings, if BOTH LINE1 and LINE2 inputs are routed to the output at the same time, then the two switches used for the connection short the two input signals together on the output pins. The shorting resistance between the two input pins is two times the bypass switch resistance (RDS(ON)). In general, this condition of shorting should be avoided, as higher drive currents are likely to occur on the circuitry that feeds these two input pins of this device.

Table 8-104 Page 0, Register 109: DAC Quiescent Current Adjustment Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D6 R/W 00 DAC Current Adjustment
00: Default
01: 50% increase in DAC reference current
10: Reserved
11: 100% increase in DAC reference current
D5–D0 R/W 00 0000 Reserved. Write only zeros to these bits.
Table 8-105 Page 0, Register 110–127: Reserved Registers
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R 0000 0000 Reserved. Do not write to these registers.
Table 8-106 Page 1, Register 0: Page Select Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D1 X 0000 000 Reserved, write only zeros to these bits.
D0 R/W 0 Page Select Bit
Writing zero to this bit sets page 0 as the active page for following register accesses. Writing a one to this bit sets page 1 as the active page for following register accesses. It is recommended that the user read this register bit back after each write, to ensure that the proper page is being accessed for future register read/writes. This register has the same functionality on page 0 and page 1.
Note: When programming any coefficient value in Page 1, the MSB register should always be written first, immediately followed by the LSB register. Even if only the MSB or LSB of the coefficient changes, both registers should be written in this sequence.
Table 8-107 Page 1, Register 1: Left-Channel Audio Effects Filter N0 Coefficient MSB Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W 0110 1011 Left-Channel Audio Effects Filter N0 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767.
Table 8-108 Page 1, Register 2: Left-Channel Audio Effects Filter N0 Coefficient LSB Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W 1110 0011 Left-Channel Audio Effects Filter N0 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767.
Table 8-109 Page 1, Register 3: Left-Channel Audio Effects Filter N1 Coefficient MSB Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W 1001 0110 Left-Channel Audio Effects Filter N1 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767.
Table 8-110 Page 1, Register 4: Left-Channel Audio Effects Filter N1 Coefficient LSB Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W 0110 0110 Left-Channel Audio Effects Filter N1 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767.
Table 8-111 Page 1, Register 5: Left-Channel Audio Effects Filter N2 Coefficient MSB Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W 0110 0111 Left-Channel Audio Effects Filter N2 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767.
Table 8-112 Page 1, Register 6: Left-Channel Audio Effects Filter N2 Coefficient LSB
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W 0101 1101 Left-Channel Audio Effects Filter N2 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767.
Table 8-113 Page 1, Register 7: Left-Channel Audio Effects Filter N3 Coefficient MSB Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W 0110 1011 Left-Channel Audio Effects Filter N3 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767.
Table 8-114 Page 1, Register 8: Left-Channel Audio Effects Filter N3 Coefficient LSB Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W 1110 0011 Left-Channel Audio Effects Filter N3 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767.
Table 8-115 Page 1, Register 9: Left-Channel Audio Effects Filter N4 Coefficient MSB Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W 1001 0110 Left-Channel Audio Effects Filter N4 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767.
Table 8-116 Page 1, Register 10: Left-Channel Audio Effects Filter N4 Coefficient LSB Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W 0110 0110 Left-Channel Audio Effects Filter N4 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767.
Table 8-117 Page 1, Register 11: Left-Channel Audio Effects Filter N5 Coefficient MSB Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W 0110 0111 Left-Channel Audio Effects Filter N5 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767.
Table 8-118 Page 1, Register 12: Left-Channel Audio Effects Filter N5 Coefficient LSB Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W 0101 1101 Left-Channel Audio Effects Filter N5 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767.
Table 8-119 Page 1, Register 13: Left-Channel Audio Effects Filter D1 Coefficient MSB Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W 0111 1101 Left-Channel Audio Effects Filter D1 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767.
Table 8-120 Page 1, Register 14: Left-Channel Audio Effects Filter D1 Coefficient LSB Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W 1000 0011 Left-Channel Audio Effects Filter D1 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767.
Table 8-121 Page 1, Register 15: Left-Channel Audio Effects Filter D2 Coefficient MSB Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W 1000 0100 Left-Channel Audio Effects Filter D2 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767.
Table 8-122 Page 1, Register 16: Left-Channel Audio Effects Filter D2 Coefficient LSB Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W 1110 1110 Left-Channel Audio Effects Filter D2 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767.
Table 8-123 Page 1, Register 17: Left-Channel Audio Effects Filter D4 Coefficient MSB Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W 0111 1101 Left-Channel Audio Effects Filter D4 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767.
Table 8-124 Page 1, Register 18: Left-Channel Audio Effects Filter D4 Coefficient LSB Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W 1000 0011 Left-Channel Audio Effects Filter D4 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767.
Table 8-125 Page 1, Register 19: Left-Channel Audio Effects Filter D5 Coefficient MSB Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W 1000 0100 Left-Channel Audio Effects Filter D5 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767.
Table 8-126 Page 1, Register 20: Left-Channel Audio Effects Filter D5 Coefficient LSB Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W 1110 1110 Left-Channel Audio Effects Filter D5 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767.
Table 8-127 Page 1, Register 21: Left-Channel De-Emphasis Filter N0 Coefficient MSB Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W 0011 1001 Left-Channel De-Emphasis Filter N0 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767.
Table 8-128 Page 1, Register 22: Left-Channel De-Emphasis Filter N0 Coefficient LSB Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W 0101 0101 Left-Channel De-Emphasis Filter N0 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767.
Table 8-129 Page 1, Register 23: Left-Channel De-Emphasis Filter N1 Coefficient MSB Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W 1111 0011 Left-Channel De-Emphasis Filter N1 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767.
Table 8-130 Page 1, Register 24: Left-Channel De-Emphasis Filter N1 Coefficient LSB Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W 0010 1101 Left-Channel De-Emphasis Filter N1 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767.
Table 8-131 Page 1, Register 25: Left-Channel De-Emphasis Filter D1 Coefficient MSB Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W 0101 0011 Left-Channel De-Emphasis Filter D1 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767.
Table 8-132 Page 1, Register 26: Left-Channel De-Emphasis Filter D1 Coefficient LSB Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W 0111 1110 Left-Channel De-Emphasis Filter D1 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767.
Table 8-133 Page 1, Register 27: Right-Channel Audio Effects Filter N0 Coefficient MSB Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W 0110 1011 Right-Channel Audio Effects Filter N0 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767.
Table 8-134 Page 1, Register 28: Right-Channel Audio Effects Filter N0 Coefficient LSB Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W 1110 0011 Right-Channel Audio Effects Filter N0 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767.
Table 8-135 Page 1, Register 29: Right-Channel Audio Effects Filter N1 Coefficient MSB Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W 1001 0110 Right-Channel Audio Effects Filter N1 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767.
Table 8-136 Page 1, Register 30: Right-Channel Audio Effects Filter N1 Coefficient LSB Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W 0110 0110 Right-Channel Audio Effects Filter N1 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767.
Table 8-137 Page 1, Register 31: Right-Channel Audio Effects Filter N2 Coefficient MSB Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W 0110 0111 Right-Channel Audio Effects Filter N2 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767.
Table 8-138 Page 1, Register 32: Right-Channel Audio Effects Filter N2 Coefficient LSB Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W 0101 1101 Right-Channel Audio Effects Filter N2 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767.
Table 8-139 Page 1, Register 33: Right-Channel Audio Effects Filter N3 Coefficient MSB Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W 0110 1011 Right-Channel Audio Effects Filter N3 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767.
Table 8-140 Page 1, Register 34: Right-Channel Audio Effects Filter N3 Coefficient LSB Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W 1110 0011 Right-Channel Audio Effects Filter N3 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767.
Table 8-141 Page 1, Register 35: Right-Channel Audio Effects Filter N4 Coefficient MSB Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W 1001 0110 Right-Channel Audio Effects Filter N4 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767.
Table 8-142 Page 1, Register 36: Right-Channel Audio Effects Filter N4 Coefficient LSB Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W 0110 0110 Right-Channel Audio Effects Filter N4 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767.
Table 8-143 Page 1, Register 37: Right-Channel Audio Effects Filter N5 Coefficient MSB Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W 0110 0111 Right-Channel Audio Effects Filter N5 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767.
Table 8-144 Page 1, Register 38: Right-Channel Audio Effects Filter N5 Coefficient LSB Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W 0101 1101 Right-Channel Audio Effects Filter N5 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767.
Table 8-145 Page 1, Register 39: Right-Channel Audio Effects Filter D1 Coefficient MSB Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W 0111 1101 Right-Channel Audio Effects Filter D1 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767.
Table 8-146 Page 1, Register 40: Right-Channel Audio Effects Filter D1 Coefficient LSB Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W 1000 0011 Right-Channel Audio Effects Filter D1 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767.
Table 8-147 Page 1, Register 41: Right-Channel Audio Effects Filter D2 Coefficient MSB Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W 1000 0100 Right-Channel Audio Effects Filter D2 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767.
Table 8-148 Page 1, Register 42: Right-Channel Audio Effects Filter D2 Coefficient LSB Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W 1110 1110 Right-Channel Audio Effects Filter D2 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767.
Table 8-149 Page 1 / Register 43: Right-Channel Audio Effects Filter D4 Coefficient MSB Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W 0111 1101 Right-Channel Audio Effects Filter D4 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767.
Table 8-150 Page 1 / Register 44: Right-Channel Audio Effects Filter D4 Coefficient LSB Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W 1000 0011 Right-Channel Audio Effects Filter D4 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767.
Table 8-151 Page 1 / Register 45: Right-Channel Audio Effects Filter D5 Coefficient MSB Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W 1000 0100 Right-Channel Audio Effects Filter D5 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767.
Table 8-152 Page 1 / Register 46: Right-Channel Audio Effects Filter D5 Coefficient LSB Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W 1110 1110 Right-Channel Audio Effects Filter D5 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767.
Table 8-153 Page 1 / Register 47: Right-Channel De-Emphasis Filter N0 Coefficient MSB Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W 0011 1001 Right-Channel De-Emphasis Filter N0 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767.
Table 8-154 Page 1 / Register 48: Right-Channel De-Emphasis Filter N0 Coefficient LSB Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W 0101 0101 Right-Channel De-Emphasis Filter N0 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767.
Table 8-155 Page 1 / Register 49: Right-Channel De-Emphasis Filter N1 Coefficient MSB Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W 1111 0011 Right-Channel De-Emphasis Filter N1 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767.
Table 8-156 Page 1 / Register 50: Right-Channel De-Emphasis Filter N1 Coefficient LSB Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W 0010 1101 Right-Channel De-Emphasis Filter N1 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767.
Table 8-157 Page 1 / Register 51: Right-Channel De-Emphasis Filter D1 Coefficient MSB Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W 0101 0011 Right-Channel De-Emphasis Filter D1 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767.
Table 8-158 Page 1 / Register 52: Right-Channel De-Emphasis Filter D1 Coefficient LSB Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W 0111 1110 Right-Channel De-Emphasis Filter D1 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767.
Table 8-159 Page 1 / Register 53: 3-D Attenuation Coefficient MSB Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W 0111 1111 3-D Attenuation Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767.
Table 8-160 Page 1 / Register 54: 3-D Attenuation Coefficient LSB Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W 1111 1111 3-D Attenuation Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767.
Table 8-161 Page 1 / Register 55–64: Reserved Registers
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R 0000 0000 Reserved. Do not write to these registers.
Table 8-162 Page 1 / Register 65: Left-Channel ADC High-Pass Filter N0 Coefficient MSB Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W 0011 1001 Left-Channel ADC High-Pass Filter N0 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767.
Table 8-163 Page 1 / Register 66: Left-Channel ADC High-Pass Filter N0 Coefficient LSB Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W 0101 0101 Left-Channel ADC High-Pass Filter N0 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767.
Table 8-164 Page 1 / Register 67: Left-Channel ADC High-Pass Filter N1 Coefficient MSB Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W 1111 0011 Left-Channel ADC High-Pass Filter N1 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767.
Table 8-165 Page 1 / Register 68: Left-Channel ADC High-Pass Filter N1 Coefficient LSB Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W 0010 1101 Left-Channel ADC High-Pass Filter N1 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767.
Table 8-166 Page 1 / Register 69: Left-Channel ADC High-Pass Filter D1 Coefficient MSB Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W 0101 0011 Left-Channel ADC High-Pass Filter D1 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767.
Table 8-167 Page 1 / Register 70: Left-Channel ADC High-Pass Filter D1 Coefficient LSB Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W 0111 1110 Left-Channel ADC High-Pass Filter D1 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767.
Table 8-168 Page 1 / Register 71: Right-Channel ADC High-Pass Filter N0 Coefficient MSB Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W 0011 1001 Right-Channel ADC High-Pass Filter N0 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767.
Table 8-169 Page 1 / Register 72: Right-Channel ADC High-Pass Filter N0 Coefficient LSB Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W 0101 0101 Right-Channel ADC High-Pass Filter N0 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767.
Table 8-170 Page 1 / Register 73: Right-Channel ADC High-Pass Filter N1 Coefficient MSB Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W 1111 0011 Right-Channel ADC High-Pass Filter N1 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767.
Table 8-171 Page 1 / Register 74: Right-Channel ADC High-Pass Filter N1 Coefficient LSB Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W 0010 1101 Right-Channel ADC High-Pass Filter N1 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767.
Table 8-172 Page 1 / Register 75: Right-Channel ADC High-Pass Filter D1 Coefficient MSB Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W 0101 0011 Right-Channel ADC High-Pass Filter D1 Coefficient MSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767.
Table 8-173 Page 1 / Register 76: Right-Channel ADC High-Pass Filter D1 Coefficient LSB Register
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R/W 0111 1110 Right-Channel ADC High-Pass Filter D1 Coefficient LSB
The 16-bit integer contained in the MSB and LSB registers for this coefficient are interpreted as a 2s-complement integer, with possible values ranging from –32,768 to 32,767.
Table 8-174 Page 1 / Registers 77–127: Reserved Registers
BIT READ/
WRITE		 RESET
VALUE		 DESCRIPTION
D7–D0 R 0000 0000 Reserved. Do not write to these registers.