SLAS510G March   2007  – February 2021 TLV320AIC3104

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (Continued)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Audio Data Serial Interface Timing Requirements
    7. 8.7 Timing Diagrams
    8. 8.8 Typical Characteristics
  9. 9 Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagrams
    3. 10.3 Feature Description
      1. 10.3.1  Hardware Reset
      2. 10.3.2  Digital Audio Data Serial Interface
        1. 10.3.2.1 Right-Justified Mode
        2. 10.3.2.2 Left-Justified Mode
        3. 10.3.2.3 I2S Mode
        4. 10.3.2.4 DSP Mode
        5. 10.3.2.5 TDM Data Transfer
      3. 10.3.3  Audio Data Converters
        1. 10.3.3.1 Audio Clock Generation
        2. 10.3.3.2 Stereo Audio ADC
          1. 10.3.3.2.1 Stereo Audio ADC High-Pass Filter
          2. 10.3.3.2.2 Automatic Gain Control (AGC)
            1. 10.3.3.2.2.1 Target Level
            2. 10.3.3.2.2.2 Attack Time
            3. 10.3.3.2.2.3 Decay Time
            4. 10.3.3.2.2.4 Noise Gate Threshold
            5. 10.3.3.2.2.5 Maximum PGA Gain Applicable
      4. 10.3.4  Stereo Audio DAC
        1. 10.3.4.1 Digital Audio Processing for Playback
        2. 10.3.4.2 Digital Interpolation Filter
        3. 10.3.4.3 Delta-Sigma Audio DAC
        4. 10.3.4.4 Audio DAC Digital Volume Control
        5. 10.3.4.5 Increasing DAC Dynamic Range
        6. 10.3.4.6 Analog Output Common-Mode Adjustment
        7. 10.3.4.7 Audio DAC Power Control
      5. 10.3.5  Audio Analog Inputs
      6. 10.3.6  Analog Fully Differential Line Output Drivers
      7. 10.3.7  Analog High-Power Output Drivers
      8. 10.3.8  Input Impedance and VCM Control
      9. 10.3.9  MICBIAS Generation
      10. 10.3.10 Short-Circuit Output Protection
      11. 10.3.11 Jack and Headset Detection
    4. 10.4 Device Functional Modes
      1. 10.4.1 Bypass Path Mode
        1. 10.4.1.1 ADC PGA Signal Bypass Path Functionality
        2. 10.4.1.2 Passive Analog Bypass During Power Down
      2. 10.4.2 Digital Audio Processing for Record Path
    5. 10.5 Programming
      1. 10.5.1 I2C Control Interface
        1. 10.5.1.1 I2C Bus Debug in a Glitched System
      2. 10.5.2 Register Map Structure
    6. 10.6 Register Maps
      1. 10.6.1 Output Stage Volume Controls
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Applications
      1. 11.2.1 Typical Connections With Headphone and External Speaker Driver in Portable Application
        1. 11.2.1.1 Design Requirements
        2. 11.2.1.2 Detailed Design Procedure
        3. 11.2.1.3 Application Curves
      2. 11.2.2 Typical Connections for AC-Coupled Headphone Output With Separate Line Outputs and External Speaker Amplifier
        1. 11.2.2.1 Design Requirements
        2. 11.2.2.2 Detailed Design Procedure
        3. 11.2.2.3 Application Curves
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Example
  14. 14Device and Documentation Support
    1. 14.1 Receiving Notification of Documentation Updates
    2. 14.2 Support Resources
    3. 14.3 Trademarks
    4. 14.4 Electrostatic Discharge Caution
    5. 14.5 Glossary

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RHB|32
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Revision History

Changes from Revision F (December 2016) to Revision G (February 2021)

  • Updated the numbering format for tables, figures, and cross-references throughout the document Go
  • Changed QFN to VQFN throughout documentGo
  • Changed Applications section Go
  • Changed Device Comparison Table: changed title, added TLV320AIC3109-Q1 rowGo
  • Deleted System Thermal Characteristics tableGo
  • Added input impedance parameter in Electrical Characteristics table: added single-ended to test conditions of first two rows, added last two rows to parameterGo
  • Deleted current consumption parameter, Stereo line in to stereo line out , no signal test conditionGo
  • Changed list of intended applications in Overview sectionGo
  • Added Functional Block Diagram With Registers figure and added caption to Functional Block Diagram figureGo
  • Added note to Audio Clock Generation sectionGo
  • Changed 2 MHz to 512 kHz in 512 kHz ≤ (PLLCLK_IN/P) ≤ 20 MHz PLL example in Audio Clock Generation sectionGo
  • Added Left Channel Signal Path and Right Channel Signal Path figures to Audio Analog Inputs sectionGo
  • Deleted Analog Input Bypass Path Functionality sectionGo
  • Changed Passive Analog Bypass Mode Configuration figure to remove LINE 2L/R input bypass Go
  • Added reset value to D0 row in Page 0, Register 9: Audio Serial Data Interface Control Register B tableGo
  • Changed D3–D0 row reset value from 000 to 0000 in Page 0, Register 37: DAC Power and Output Driver Control Register tableGo
  • Changed reset value from 1 to 0 and changed description of bit D1 in Page 0, Register 51: HPLOUT Output Level Control Register Go
  • Changed reset value from 1 to 0 and changed description of bit D1 in Page 0, Register 58: HPLCOM Output Level Control Register Go
  • Changed reset value from 1 to 0 and changed description of bit D1 in Page 0, Register 65: HPROUT Output Level Control Register Go
  • Changed reset value from 1 to 0 and changed description of bit D1 in Page 0, Register 72: HPRCOM Output Level Control Register Go
  • Changed reset value from 1 to 0 and changed description of bit D1 in Page 0, Register 86: LEFT_LOP/M Output Level Control Register Go
  • Changed Read/Write value from R to R/W in bit D0 of Page 0, Register 86: LEFT_LOP/M Output Level Control Register Go
  • Changed reset value from 1 to 0 and changed description of bit D1 in Page 0, Register 93: RIGHT_LOP/M Output Level Control Register Go
  • Changed Read/Write value from R to R/W in bit D0 of Page 0, Register 93: RIGHT_LOP/M Output Level Control Register Go
  • Changed Read/Write value from R to R/W in bit D0 of Page 0, Register 96: Sticky Interrupt Flags Register Go
  • Changed reset value from 00 to 11 and changed description of bits D5–D4 in Page 0, Register 107: New Programmable ADC Digital Path and I2C Bus Condition Register Go
  • Changed description of bits D6 and D2 in Page 0, Register 108: Passive Analog Signal Bypass Selection During Power Down Register Go
  • Changed Cell Phone to Portable in title of Typical Connections With Headphone and External Speaker Driver in Portable Application section and in title of Typical Connections With Headphone and External Speaker Driver in Portable Applications figureGo

Changes from Revision E (November 2016) to Revision F (December 2016)

  • Deleted paragraph "Another programmable option..." from the Input Impedance and VCM Control sectionGo