SLAS510G March   2007  – February 2021 TLV320AIC3104

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (Continued)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Audio Data Serial Interface Timing Requirements
    7. 8.7 Timing Diagrams
    8. 8.8 Typical Characteristics
  9. 9 Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagrams
    3. 10.3 Feature Description
      1. 10.3.1  Hardware Reset
      2. 10.3.2  Digital Audio Data Serial Interface
        1. 10.3.2.1 Right-Justified Mode
        2. 10.3.2.2 Left-Justified Mode
        3. 10.3.2.3 I2S Mode
        4. 10.3.2.4 DSP Mode
        5. 10.3.2.5 TDM Data Transfer
      3. 10.3.3  Audio Data Converters
        1. 10.3.3.1 Audio Clock Generation
        2. 10.3.3.2 Stereo Audio ADC
          1. 10.3.3.2.1 Stereo Audio ADC High-Pass Filter
          2. 10.3.3.2.2 Automatic Gain Control (AGC)
            1. 10.3.3.2.2.1 Target Level
            2. 10.3.3.2.2.2 Attack Time
            3. 10.3.3.2.2.3 Decay Time
            4. 10.3.3.2.2.4 Noise Gate Threshold
            5. 10.3.3.2.2.5 Maximum PGA Gain Applicable
      4. 10.3.4  Stereo Audio DAC
        1. 10.3.4.1 Digital Audio Processing for Playback
        2. 10.3.4.2 Digital Interpolation Filter
        3. 10.3.4.3 Delta-Sigma Audio DAC
        4. 10.3.4.4 Audio DAC Digital Volume Control
        5. 10.3.4.5 Increasing DAC Dynamic Range
        6. 10.3.4.6 Analog Output Common-Mode Adjustment
        7. 10.3.4.7 Audio DAC Power Control
      5. 10.3.5  Audio Analog Inputs
      6. 10.3.6  Analog Fully Differential Line Output Drivers
      7. 10.3.7  Analog High-Power Output Drivers
      8. 10.3.8  Input Impedance and VCM Control
      9. 10.3.9  MICBIAS Generation
      10. 10.3.10 Short-Circuit Output Protection
      11. 10.3.11 Jack and Headset Detection
    4. 10.4 Device Functional Modes
      1. 10.4.1 Bypass Path Mode
        1. 10.4.1.1 ADC PGA Signal Bypass Path Functionality
        2. 10.4.1.2 Passive Analog Bypass During Power Down
      2. 10.4.2 Digital Audio Processing for Record Path
    5. 10.5 Programming
      1. 10.5.1 I2C Control Interface
        1. 10.5.1.1 I2C Bus Debug in a Glitched System
      2. 10.5.2 Register Map Structure
    6. 10.6 Register Maps
      1. 10.6.1 Output Stage Volume Controls
  11. 11Application and Implementation
    1. 11.1 Application Information
    2. 11.2 Typical Applications
      1. 11.2.1 Typical Connections With Headphone and External Speaker Driver in Portable Application
        1. 11.2.1.1 Design Requirements
        2. 11.2.1.2 Detailed Design Procedure
        3. 11.2.1.3 Application Curves
      2. 11.2.2 Typical Connections for AC-Coupled Headphone Output With Separate Line Outputs and External Speaker Amplifier
        1. 11.2.2.1 Design Requirements
        2. 11.2.2.2 Detailed Design Procedure
        3. 11.2.2.3 Application Curves
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
    2. 13.2 Layout Example
  14. 14Device and Documentation Support
    1. 14.1 Receiving Notification of Documentation Updates
    2. 14.2 Support Resources
    3. 14.3 Trademarks
    4. 14.4 Electrostatic Discharge Caution
    5. 14.5 Glossary

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RHB|32
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.5 Electrical Characteristics

At 25°C, AVDD = DRVDD = IOVDD = 3.3 V, DVDD = 1.8 V, fS = 48 kHz, 16-bit audio data (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AUDIO ADC
Input signal level Single-ended 0.707 VRMS
SNR Signal-to-noise ratio(1)(2) A-weighted, fS = 48 ksps, 0-dB PGA gain, inputs ac-shorted to ground 80 92 dB
Dynamic range(1)(2) fS = 48 ksps; 0-dB PGA gain; 1-kHz, –60-dB full-scale input signal 93 dB
THD Total harmonic distortion fS = 48 ksps; 0-dB PGA gain; 1-kHz, –2-dB full-scale input signal –89 –75 dB
PSRR Power-supply rejection ratio 217-Hz signal applied to DRVDD 55 dB
1-kHz signal applied to DRVDD 44
Input channel separation 1-kHz, –2-dB full-scale signal, MIC1L to MIC1R –71 dB
Gain error fS = 48 ksps; 0-dB PGA gain; 1-kHz, –2-dB full-scale input signal 0.82 dB
ADC programmable-gain amplifier maximum gain 1-kHz input tone 59.5 dB
ADC programmable-gain amplifier step size 0.5 dB
Input resistance MIC1L/MIC1R inputs routed to single ADC single-ended
input mix attenuation = 0 dB		 20 kΩ
MIC1L/MIC1R inputs routed to single ADC single-ended
input mix attenuation = 12 dB		 80
MIC2L/MIC2R inputs routed to single ADC
input mix attenuation = 0 dB		 20
MIC2L/MIC2R inputs routed to single ADC
input mix attenuation = 12 dB		 80
MIC1L/MIC1R inputs routed to single ADC differential
input mix attenuation = 0 dB		 80
MIC1L/MIC1R inputs routed to single ADC differential
input mix attenuation = 12 dB		 320
Input capacitance MIC1/LINE1 inputs 10 pF
Input level control minimum attenuation setting 0 dB
Input level control maximum attenuation setting 12 dB
Input level control attenuation step size 1.5 dB
ANALOG PASSTHROUGH MODE
RDS(on) Input-to-output switch resistance MIC1/LIN1 to LINEOUT 330 Ω
MIC2/LIN2 to LINEOUT 330
INPUT SIGNAL LEVEL, DIFFERENTIAL
SNR Signal-to-noise ratio A-weighted, fS = 48 ksps, 0 dB PGA gain, inputs ac-shorted to ground 92 dB
THD Total harmonic distortion fS = 48 kHz; 0-dB PGA gain, 1-kHz, –2-dB full-scale input signal –94 dB
ADC DIGITAL DECIMATION FILTER, fS = 48 kHz
Filter gain From 0 to 0.39 fS ±0.1 dB
At 0.4125 fS –0.25
At 0.45 fS –3
At 0.5 fS –17.5
From 0.55 fS to 64 fS –75
Filter group delay 17 / fS s
MICROPHONE BIAS
Bias voltage Programmable setting = 2 V 2 V
Programmable setting = 2.5 V 2.3 2.455 2.7
Programmable setting = DRVDD DRVDD – 0.24
Current sourcing Programmable setting = 2.5 V 4 mA
AUDIO DAC – DIFFERENTIAL LINE OUTPUT, RLOAD = 10 kΩ
Full-scale output voltage 0-dB input full-scale signal, output common-mode setting = 1.35 V, output volume control = 0 dB 1.414 VRMS
4 VPP
Signal-to-noise ratio(3) A-weighted, fS = 48 kHz, output volume control = 0 dB, no input signal, referenced to full-scale input level 90 102 dB
Dynamic range A-weighted, fS = 48 kHz, –60-dB input full-scale signal, output volume control = 0 dB, output common-mode setting = 1.35 V 97 dB
Total harmonic distortion fS = 48 kHz; 0-dB, 1-kHz input full-scale signal; output volume control = 0 dB; output common-mode setting = 1.35 V –95 –75 dB
PSRR Power-supply rejection ratio 217-Hz signal applied to DRVDD, AVDD 78 dB
1-kHz signal applied to DRVDD, AVDD 80
DAC channel separation 0-dB full-scale input signal between left and right lineout 86 dB
DAC inter-channel gain mismatch 1-kHz input, 0-dB gain 0.1 dB
DAC gain error 0-dB, 1-kHz input full-scale signal; output volume control = 0 dB; output common-mode setting = 1.35 V; fS = 48 kHz –0.2 dB
AUDIO DAC – SINGLE-ENDED LINE OUTPUT, RLOAD = 10 kΩ
Full-scale output voltage 0-dB input full-scale signal, output common-mode setting = 1.35 V, output volume control = 0 dB 0.707 VRMS
SNR Signal-to-noise ratio A-weighted, fS = 48 kHz, output volume control = 0 dB, no input signal, referenced to full-scale input level 96 dB
A-weighted, fS = 48 kHz, output volume control = 0 dB, no input signal, referenced to full-scale input level, 50% DAC current-boost mode 97
Dynamic range A-weighted, fS = 48 kHz, –60-dB input full-scale signal, output volume control = 0 dB, output common-mode setting = 1.35 V 91 dB
THD Total harmonic distortion fS = 48 kHz, 0-dB input full-scale signal, output volume control = 0 dB, output common-mode setting = 1.35 V –71 –65 dB
PSRR Power-supply rejection ratio 217-Hz signal applied to DRVDD, AVDD 43 dB
1-kHz signal applied to DRVDD, AVDD 41
DAC channel separation Right headphone out 89 dB
DAC gain error 0-dB, 1-kHz input full-scale signal; output volume control = 0 dB; output common-mode setting = 1.35 V; fS = 48 kHz –0.85 dB
AUDIO DAC – SINGLE-ENDED HEADPHONE OUTPUT, RLOAD = 16 Ω
Full-scale output voltage 0-dB input full-scale signal, output common-mode setting = 1.35 V, output volume control = 0 dB 0.707 VRMS
SNR Signal-to-noise ratio A-weighted, fS = 48 kHz, output volume control = 0 dB, no input signal, referenced to full-scale input level 96 dB
A-weighted, fS = 48 kHz, output volume control = 0 dB, no input signal, referenced to full-scale input level, 50% DAC current-boost mode 97
Dynamic range A-weighted, fS = 48 kHz, –60-dB input full-scale signal, output volume control = 0 dB, output common-mode setting = 1.35 V 91 dB
THD Total harmonic distortion fS = 48 kHz, 0-dB input full-scale signal, output volume control = 0 dB, output common-mode setting = 1.35 V –71 –65 dB
PSRR Power-supply rejection ratio 217-Hz signal applied to DRVDD, AVDD 43 dB
1-kHz signal applied to DRVDD, AVDD 41
DAC channel separation Right headphone out 89 dB
DAC gain error 0-dB, 1-kHz input full-scale signal; output volume control = 0 dB; output common-mode setting = 1.35 V; fS = 48 kHz –0.85 dB
DAC DIGITAL INTERPOLATION – FILTER fS = 48 kHz
Pass band 0 0.45 fS Hz
Pass-band ripple ±0.06 dB
Transition band 0.45 fS 0.55 fS Hz
Stop band 0.55 fS 7.5 fS Hz
Stop-band attenuation 65 dB
Group delay 21 / fS s
STEREO HEADPHONE DRIVER – AC-COUPLED OUTPUT CONFIGURATION(3)
0-dB full-scale output voltage 0-dB gain to high-power outputs. Output common-mode voltage setting = 1.35 V 0.707 VRMS
Programmable output common-mode voltage (applicable to line outputs also) First option 1.35 V
Second option 1.5
Third option 1.65
Fourth option 1.8
Maximum programmable output level control gain 9 dB
Programmable output level control gain step size 1 dB
PO Maximum output power RL = 32 Ω 15 mW
RL = 16 Ω 30
Signal-to-noise ratio(4) A-weighted 94 dB
Total harmonic distortion 1-kHz output, PO = 5 mW, RL = 32 Ω –77 dB%
0.014
1-kHz output, PO = 10 mW, RL = 32 Ω –76
0.016
1-kHz output, PO = 10 mW, RL = 16 Ω –73
0.022
1-kHz output, PO = 20 mW, RL = 16 Ω –71
0.028
Channel separation 1-kHz, 0-dB input 90 dB
Power supply rejection ratio 217 Hz, 100 mVpp on AVDD, DRVDD1/2 48 dB
Mute attenuation 1-kHz output 107 dB
DIGITAL I/O
VIL Input low level –0.3 0.3 IOVDD V
VIH Input high level (5) IOVDD > 1.6 V 0.7 IOVDD V
IOVDD ≤ 1.6 V 1.1
VOL Output low level 0.1 IOVDD V
VOH Output high level 0.8 IOVDD V
CURRENT CONSUMPTION – DRVDD = AVDD = IOVDD = 3.3 V, DVDD = 1.8 V
IIN IDRVDD + IAVDD RESET held low 0.1 μA
IDVDD 0.2
IDRVDD + IAVDD Mono ADC record, fS = 8 ksps, I2S slave, AGC off, no signal 2.15 mA
IDVDD 0.48
IDRVDD + IAVDD Stereo ADC record, fS = 8 ksps, I2S slave, AGC off, no signal 4.1
IDVDD 0.62
IDRVDD + IAVDD Stereo ADC record, fS = 48 ksps, I2S slave, AGC off, no signal 4.31(6)
IDVDD 2.45(6)
IDRVDD + IAVDD Stereo DAC playback to lineout, analog mixer bypassed, fS = 48 ksps, I2S slave 3.5
IDVDD 2.3
IDRVDD + IAVDD Stereo DAC playback to lineout, fS = 48 ksps, I2S slave, no signal 4.9
IDVDD 2.3
IDRVDD + IAVDD Stereo DAC playback to stereo single-ended headphone, fS = 48 ksps, I2S slave, no signal 6.7
IDVDD 2.3
IDRVDD + IAVDD Extra power when PLL enabled 1.4
IDVDD 0.9
IDRVDD + IAVDD All blocks powered down. Headset detection enabled, headset not inserted 28 μA
IDVDD 2
(1) Ratio of output level with 1-kHz full-scale sine-wave input, to the output level with the inputs short-circuited, measured A-weighted over a 20-Hz to 20-kHz bandwidth using an audio analyzer.
(2) All performance measurements done with 20-kHz low-pass filter and, where noted, A-weighted filter. Failure to use such a filter may result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter removes out-of-band noise, which, although not audible, may affect dynamic specification values.
(3) Unless otherwise noted, all measurements use output common-mode voltage setting of 1.35 V, 0-dB output level control gain, 16-Ω single-ended load.
(4) Ratio of output level with a 1-kHz full-scale input, to the output level playing an all-zero signal, measured A-weighted over a 20-Hz to 20-kHz bandwidth.
(5) When IOVDD < 1.6 V, minimum VIH is 1.1 V.
(6) Additional power is consumed when the PLL is powered.