SLAS663C August   2009  – June 2016 TLV320AIC3106-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (Continued)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information
    5. 8.5  Electrical Characteristics
    6. 8.6  Switching Characteristics I2S/LJF/RJF In Master Mode
    7. 8.7  Switching Characteristics I2S/LJF/RJF In Slave Mode
    8. 8.8  Switching Characteristics DSP In Master Mode
    9. 8.9  Switching Characteristics DSP In Slave Mode
    10. 8.10 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Audio Data Converters
      2. 9.3.2  Stereo Audio ADC
        1. 9.3.2.1 Stereo Audio ADC High-Pass Filter
      3. 9.3.3  Automatic Gain Control (AGC)
      4. 9.3.4  Stereo Audio DAC
      5. 9.3.5  Digital Audio Processing For Playback
      6. 9.3.6  Digital Interpolation Filter
      7. 9.3.7  Delta-Sigma Audio Dac
      8. 9.3.8  Audio Dac Digital Volume Control
      9. 9.3.9  Analog Output Common-Mode Adjustment
      10. 9.3.10 Audio DAC Power Control
      11. 9.3.11 Audio Analog Inputs
      12. 9.3.12 Analog Input Bypass Path Functionality
      13. 9.3.13 ADC PGA Signal Bypass Path Functionality
      14. 9.3.14 Input Impedance and VCM Control
      15. 9.3.15 MICBIAS Generation
      16. 9.3.16 Analog Fully Differential Line Output Drivers
      17. 9.3.17 Analog High Power Output Drivers
      18. 9.3.18 Short Circuit Output Protection
      19. 9.3.19 Jack and Headset Detection
      20. 9.3.20 General-Purpose I/O
    4. 9.4 Device Functional Modes
      1. 9.4.1 Digital Audio Processing For Record Path
      2. 9.4.2 Increasing DAC Dynamic Range
      3. 9.4.3 Passive Analog Bypass During Powerdown
      4. 9.4.4 Digital Microphone Connectivity
    5. 9.5 Programming
      1. 9.5.1  Hardware Reset
      2. 9.5.2  Digital Control Serial Interface
        1. 9.5.2.1 SPI Control Mode
        2. 9.5.2.2 SPI Communication Protocol
          1. 9.5.2.2.1 Limitation On Register Writing
        3. 9.5.2.3 Continuous Read and Write Operation
      3. 9.5.3  I2C Control Mode
      4. 9.5.4  I2C Bus Debug In A Glitched System
      5. 9.5.5  Digital Audio Data Serial Interface
      6. 9.5.6  Right-Justified Mode
      7. 9.5.7  Left-Justified Mode
      8. 9.5.8  I2S Mode
      9. 9.5.9  DSP Mode
      10. 9.5.10 TDM Data Transfer
      11. 9.5.11 Audio Clock Generation
    6. 9.6 Register Maps
      1. 9.6.1 Output Stage Volume Controls
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Receiving Notification of Documentation Updates
    2. 13.2 Community Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, And Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Description (Continued)

The TLV320AIC3106-Q1 contains four high-power output drivers as well as three fully differential output drivers. The high-power output drivers are capable of driving a variety of load configurations, including up to four channels of single-ended 16-Ω headphones using AC-coupling capacitors, or stereo 16-Ω headphones in a capacitorless output configuration. These parameters enable the TLV320AIC3106-Q1 to act as an interface from the MCU to the speaker amplifiers, such as the TPA3111D1-Q1, in various audio applications in infotainment and clusters.

The stereo audio DAC supports sampling rates from 8 kHz to 96 kHz and includes programmable digital filtering in the DAC path for 3D, bass, treble, midrange effects, speaker equalization, and de-emphasis for 32-kHz, 44.1‑kHz, and 48-kHz rates. The stereo audio ADC supports sampling rates from 8 kHz to 96 kHz and is preceded by programmable gain amplifiers or AGC that can provide up to 59.5-dB analog gain for low-level microphone inputs. The TLV320AIC3106-Q1 provides an extremely high range of programmability for both attack (8 ms to 1408 ms) and for decay (0.05 s to 22.4 s). This extended AGC range allows the AGC to be tuned for many types of applications.

The serial control bus supports SPI or I2C protocols, while the serial audio data bus is programmable for I2S, left/right-justified, DSP, or TDM modes. A highly programmable PLL is included for flexible clock generation and support for all standard audio rates from a wide range of available MCLKs, varying from 512 kHz to 50 MHz, with special attention paid to the most popular cases of 12-MHz, 13-MHz, 16-MHz, 19.2-MHz, and 19.68-MHz system clocks.

The TLV320AIC3106-Q1 operates from an analog supply of 2.7 V to 3.6 V, a digital core supply of 1.65 V to 1.95 V, and a digital I/O supply of 1.1 V to 3.6 V. The device is available in the 7-mm × 7-mm, 48-lead VQFN (RGZ) package.