SLAS653C February   2010  – February 2017 TLV320AIC3120

PRODUCTION DATA.  

  1. 1 Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Functional Block Diagram
  2. 2 Revision History
  3. 3  Device Comparison
  4. 4 Pin Configuration and Functions
    1. 4.1 Pin Attributes
  5. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Power Dissipation Ratings
    7. 5.7  I2S, LJF, and RJF Timing in Master Mode
    8. 5.8  I2S, LJF, and RJF Timing in Slave Mode
    9. 5.9  DSP Timing in Master Mode
    10. 5.10 DSP Timing in Slave Mode
    11. 5.11 I2C Interface Timing
    12. 5.12 Typical Characteristics
      1. 5.12.1 Audio ADC Performance
      2. 5.12.2 DAC Performance
      3. 5.12.3 Class-D Speaker Driver Performance
      4. 5.12.4 Analog Bypass Performance H
      5. 5.12.5 MICBIAS Performance H
  6. 6 Parameter Measurement Information
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Power-Supply Sequence
      2. 7.3.2  Reset
      3. 7.3.3  Device Start-Up Lockout Times
      4. 7.3.4  PLL Start-Up
      5. 7.3.5  Power-Stage Reset
      6. 7.3.6  Software Power Down
      7. 7.3.7  Audio Analog I/O
      8. 7.3.8  miniDSP
        1. 7.3.8.1 Software
      9. 7.3.9  Digital Processing Low-Power Modes
        1. 7.3.9.1 ADC, Mono, 48 kHz, DVDD = 1.8 V, AVDD = 3.3 V
        2. 7.3.9.2 ADC, Mono, 8 kHz, DVDD = 1.8 V, AVDD = 3.3 V
        3. 7.3.9.3 DAC Playback on Headphones, Mono, 48 kHz, DVDD = 1.8 V, AVDD = 3.3 V, HPVDD = 3.3 V
        4. 7.3.9.4 DAC Playback on Headphones, Mono, 8 kHz, DVDD = 1.8 V, AVDD = 3.3 V, HPVDD = 3.3 V
      10. 7.3.10 Audio ADC and Analog Inputs
        1. 7.3.10.1 MICBIAS and Microphone Preamplifier
        2. 7.3.10.2 Automatic Gain Control (AGC)
        3. 7.3.10.3 Delta-Sigma ADC
        4. 7.3.10.4 ADC Decimation Filtering and Signal Processing
          1. 7.3.10.4.1 ADC Processing Blocks
          2. 7.3.10.4.2 ADC Processing Blocks - Signal Chain Details
            1. 7.3.10.4.2.1 First-Order IIR, AGC, Filter A
            2. 7.3.10.4.2.2 Five Biquads, First-Order IIR, AGC, Filter A
            3. 7.3.10.4.2.3 25-Tap FIR, First-Order IIR, AGC, Filter A
            4. 7.3.10.4.2.4 First-Order IIR, AGC, Filter B
            5. 7.3.10.4.2.5 Three Biquads, First-Order IIR, AGC, Filter B
            6. 7.3.10.4.2.6 20-Tap FIR, First-Order IIR, AGC, Filter B
            7. 7.3.10.4.2.7 First-Order IIR, AGC, Filter C
            8. 7.3.10.4.2.8 Five Biquads, First-Order IIR, AGC, Filter C
            9. 7.3.10.4.2.9 25-Tap FIR, First-Order IIR, AGC, Filter C
          3. 7.3.10.4.3 User-Programmable Filters
            1. 7.3.10.4.3.1 First-Order IIR Section
            2. 7.3.10.4.3.2 Biquad Section
            3. 7.3.10.4.3.3 FIR Section
          4. 7.3.10.4.4 ADC Digital Decimation Filter Characteristics
            1. 7.3.10.4.4.1 Decimation Filter A
            2. 7.3.10.4.4.2 Decimation Filter B
            3. 7.3.10.4.4.3 Decimation Filter C
          5. 7.3.10.4.5 ADC Data Interface
        5. 7.3.10.5 Updating ADC Digital Filter Coefficients During Record
        6. 7.3.10.6 Digital Microphone Function
        7. 7.3.10.7 DC Measurement
        8. 7.3.10.8 ADC Setup
      11. 7.3.11 Example Register Setup to Record Analog Data Through ADC to Digital Out
      12. 7.3.12 Audio DAC and Audio Analog Outputs
        1. 7.3.12.1  DAC
          1. 7.3.12.1.1 DAC Processing Blocks
          2. 7.3.12.1.2 DAC Processing Blocks — Signal Chain Details
            1. 7.3.12.1.2.1 Three Biquads, Filter A
            2. 7.3.12.1.2.2 Six Biquads, First-Order IIR, DRC, Filter A or B
            3. 7.3.12.1.2.3 Six Biquads, First-Order IIR, Filter A or B
            4. 7.3.12.1.2.4 IIR, Filter B or C
            5. 7.3.12.1.2.5 Four Biquads, DRC, Filter B
            6. 7.3.12.1.2.6 Four Biquads, Filter B
            7. 7.3.12.1.2.7 Four Biquads, First-Order IIR, DRC, Filter C
            8. 7.3.12.1.2.8 Four Biquads, First-Order IIR, Filter C
            9. 7.3.12.1.2.9 Five Biquads, DRC, Beep Generator, Filter A
          3. 7.3.12.1.3 DAC User-Programmable Filters
            1. 7.3.12.1.3.1 First-Order IIR Section
            2. 7.3.12.1.3.2 Biquad Section
          4. 7.3.12.1.4 DAC Interpolation Filter Characteristics
            1. 7.3.12.1.4.1 Interpolation Filter A
            2. 7.3.12.1.4.2 Interpolation Filter B
            3. 7.3.12.1.4.3 Interpolation Filter C
        2. 7.3.12.2  DAC Digital-Volume Control
        3. 7.3.12.3  Volume Control Pin
        4. 7.3.12.4  Dynamic Range Compression
          1. 7.3.12.4.1 DRC Threshold
          2. 7.3.12.4.2 DRC Hysteresis
          3. 7.3.12.4.3 DRC Hold
          4. 7.3.12.4.4 DRC Attack Rate
          5. 7.3.12.4.5 DRC Decay Rate
          6. 7.3.12.4.6 Example Setup for DRC
        5. 7.3.12.5  Headset Detection
        6. 7.3.12.6  Interrupts
        7. 7.3.12.7  Key-Click Functionality With Beep Generator (PRB_P25)
        8. 7.3.12.8  Programming DAC Digital Filter Coefficients
        9. 7.3.12.9  Updating DAC Digital Filter Coefficients During PLAY
        10. 7.3.12.10 Digital Mixing and Routing
        11. 7.3.12.11 Analog Audio Routing
          1. 7.3.12.11.1 Analog Output Volume Control
          2. 7.3.12.11.2 Headphone Analog-Output Volume Control
          3. 7.3.12.11.3 Class-D Speaker Analog Output Volume Control
        12. 7.3.12.12 Analog Outputs
          1. 7.3.12.12.1 Headphone Drivers
          2. 7.3.12.12.2 Speaker Drivers
        13. 7.3.12.13 Audio-Output Stage-Power Configurations
        14. 7.3.12.14 DAC Setup
        15. 7.3.12.15 Example Register Setup to Play Digital Data Through DAC and Headphone/Speaker Outputs
      13. 7.3.13 CLOCK Generation and PLL
        1. 7.3.13.1 PLL
      14. 7.3.14 Timer
      15. 7.3.15 Digital Audio and Control Interface
        1. 7.3.15.1 Digital Audio Interface
          1. 7.3.15.1.1 Right-Justified Mode
          2. 7.3.15.1.2 Left-Justified Mode
          3. 7.3.15.1.3 I2S Mode
          4. 7.3.15.1.4 DSP Mode
        2. 7.3.15.2 Primary and Secondary Digital Audio Interface Selection
        3. 7.3.15.3 Control Interface
          1. 7.3.15.3.1 I2C Control Mode
    4. 7.4 Register Map
      1. 7.4.1 TLV320AIC3120 Register Map
      2. 7.4.2 Registers
        1. 7.4.2.1  Control Registers, Page 0 (Default Page): Clock Multipliers, Dividers, Serial Interfaces, Flags, Interrupts, and GPIOs
        2. 7.4.2.2  Control Registers, Page 1: DAC and ADC Routing, PGA, Power-Controls, and MISC Logic-Related Programmability
        3. 7.4.2.3  Control Registers, Page 3: MCLK Divider for Programmable Delay Timer
        4. 7.4.2.4  Control Registers, Page 4: ADC Digital Filter Coefficients
        5. 7.4.2.5  Control Registers, Page 5: ADC Programmable Coefficients RAM (65:127)
        6. 7.4.2.6  Control Registers, Page 8: DAC Programmable Coefficients RAM Buffer A (1:63)
        7. 7.4.2.7  Control Registers, Page 9: DAC Programmable Coefficients RAM Buffer A (65:127)
        8. 7.4.2.8  Control Registers, Page 10: DAC Programmable Coefficients RAM Buffer A (129:191)
        9. 7.4.2.9  Control Registers, Page 11: DAC Programmable Coefficients RAM Buffer A (193:255)
        10. 7.4.2.10 Control Registers, Page 12: DAC Programmable Coefficients RAM Buffer B (1:63)
        11. 7.4.2.11 Control Registers, Page 13: DAC Programmable Coefficients RAM Buffer B (65:127)
        12. 7.4.2.12 Control Registers, Page 14: DAC Programmable Coefficients RAM Buffer B (129:191)
        13. 7.4.2.13 Control Registers, Page 15: DAC Programmable Coefficients RAM Buffer B (193:255)
        14. 7.4.2.14 Control Registers, Page 32: ADC DSP Engine Instruction RAM (0:31)
          1. 7.4.2.14.1 Page 32 / Register 5 (0x05) Through Page 32 / Register 97 (0x61)
        15. 7.4.2.15 Control Registers, Pages 33-43: ADC DSP Engine Instruction RAM (32:63) Through (352:383)
        16. 7.4.2.16 Control Registers, Page 64: DAC DSP Engine Instruction RAM (0:31)
          1. 7.4.2.16.1 Page 64 / Register 5 Through Page 64 / Register 97
        17. 7.4.2.17 Control Registers, Pages 65 to 95: DAC DSP Engine Instruction RAM (32:63) Through (992:1023)
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical Packaging and Orderable Information
    1. 12.1 Packaging Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

2 Revision History

Changes from B Revision (August 2016) to C Revision

  • Added: Page 0 / Register 51 (0x33): GPIO1 In/Out Pin ControlGo

Changes from A Revision (May 2012) to B Revision

  • Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section.Go
  • Deleted SPRVDD and SPRVSS pins from the Pin Functions tableGo
  • Changed references to SPLVDD in Typical Performance graphs to SPKVDDGo
  • Added Power-Supply Sequence section to the Device Initialization sectionGo
  • Added the reference to the PGA Gain Versus Input Impedance table in the MICBIAS and Microphone Preamplifier sectionGo
  • Changed SDIN terminal to DIN in Figure 7-16Go
  • Changed Section 7.3.12.1.2 diagrams for PRB_P2/5/8/10/13/15/18/21/24/25 to reflect that the DRC_HPF filter cannot be bypassed when the DRC is turned off Go
  • Added sequence for inserting a beep in the middle of an already-playing signal and note text following script in the Key-Click Functionality With Digital Sine-Wave Generator (PRB_P25) sectionGo
  • Changed references of HPLOUT to HPOUT in Section 7.3.12.12.1 sectionGo
  • Added PRB modes text to note for Page 0 / Register 20Go
  • Added PRB modes text to Page 0 / Register 21. Also added Page 0 / Register 21 programmed value noteGo
  • Added D(3:0) note to Page 0 / Register 22Go
  • Changed last line to "10111-11000: Reserved. Do not use." "11001: DAC Signal Processing Block PRB_P25" "11010-11111: Reserved. Do not use."Go
  • Changed values in Page 0 / Register 69 (0x45): DRC Control 2Go
  • Changed Page 0, Register 70, bit D3-D0 decay rate value for 0000 from DR = 1.5625e–3 to DR = 0.015625Go
  • Switched D1 and D0 descriptions so that D1 is for SP and D0 is for HP in Page 1 / Register 30 tableGo
  • Changed Page 1 / Register 40, D1 to reservedGo
  • Changed references to TLV320AIC3111 device to the TLV320AIC3120 device throughout the REGISTER MAP section Go

Changes from * Revision (February 2010) to A Revision

  • Added PGA Gain table to data sheetGo
  • Added PRB_P25 and values to Table 7-20.Go
  • Added Section 7.3.12.1.2.9 and Signal Chain with beep generator imageGo
  • Added section Section 7.3.12.7 after Interrupts sectionGo
  • Added D6-D0 to the Register Value columns, and changed the Analog Attenuation columns to Analog GainGo
  • Added table note to Analog Volume Control for Headphone and Speaker Outputs (for D7 = 1) tableGo
  • Changed "page 0 / register 44" to " page 1 / register 44" in Headphone Drivers section Go
  • Changed max AOSR values in Clock Distribution Tree image from 1023, 1024 to 255, 256.Go
  • Changed PLL conditions under Equation 10 and Equation 11Go
  • Added Timer sectionGo
  • Deleted the Page 0 / Register 71–Page 0 / Register 80 table and added Beep Generator bit registers from SLAS659A (Page 0 / Register 71–80).Go
  • Modified Page 0 / Register 80 title from Page 0 / Register 80-115: Reserved to Page 0 / Register 80: Reserved.Go
  • Corrected values in Description column for bits D6–D0 of Page 0 / Register 83Go
  • Changed Bit D0 = 1 to Reserved.Go
  • Deleted references to Analog Volume Control (D7 = 0) table from Page 1 / Register 36 and Page 1 / Register 38Go
  • Changed Added table note following Page 1 / Register 40Go
  • Deleted one of the table notes from Page 1/ Register 48 and Page 1 / Register 49Go