SLOS602E September   2008  – September 2019 TLV320AIC3204

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Block Diagram
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics, ADC
    6. 7.6  Electrical Characteristics, Bypass Outputs
    7. 7.7  Electrical Characteristics, Microphone Interface
    8. 7.8  Electrical Characteristics, Audio DAC Outputs
    9. 7.9  Electrical Characteristics, LDO
    10. 7.10 Electrical Characteristics, Misc.
    11. 7.11 Electrical Characteristics, Logic Levels
    12. 7.12 I2S LJF and RJF Timing in Master Mode (see )
    13. 7.13 I2S LJF and RJF Timing in Slave Mode (see )
    14. 7.14 DSP Timing in Master Mode (see )
    15. 7.15 DSP Timing in Slave Mode (see )
    16. 7.16 Digital Microphone PDM Timing (see )
    17. 7.17 I2C Interface Timing
    18. 7.18 SPI Interface Timing (See )
    19. 7.19 Typical Characteristics
    20. 7.20 Typical Characteristics, FFT
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Device Connections
        1. 9.3.1.1 Digital Pins
          1. 9.3.1.1.1 Multifunction Pins
        2. 9.3.1.2 Analog Pins
      2. 9.3.2 Analog Audio IO
        1. 9.3.2.1 Analog Low Power Bypass
        2. 9.3.2.2 ADC Bypass Using Mixer Amplifiers
        3. 9.3.2.3 Headphone Outputs
        4. 9.3.2.4 Line Outputs
      3. 9.3.3 ADC
        1. 9.3.3.1 ADC Processing
          1. 9.3.3.1.1 ADC Processing Blocks
      4. 9.3.4 DAC
        1. 9.3.4.1 DAC Processing Blocks
      5. 9.3.5 PowerTune
      6. 9.3.6 Digital Audio IO Interface
      7. 9.3.7 Clock Generation and PLL
      8. 9.3.8 Control Interfaces
        1. 9.3.8.1 I2C Control
        2. 9.3.8.2 SPI Control
    4. 9.4 Device Functional Modes
    5. 9.5 Register Map
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
        1. 10.2.1.1 Reference Filtering Capacitor
        2. 10.2.1.2 MICBIAS
      2. 10.2.2 Detailed Design Procedures
        1. 10.2.2.1 Analog Input Connection
        2. 10.2.2.2 Analog Output Connection
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Community Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.6 Electrical Characteristics, Bypass Outputs

At 25°C, AVDD, DVDD, IOVDD = 1.8V, LDOIN = 3.3V, AVDD and DVDD LDO disabled, fs (Audio) = 48kHz, Cref = 10µF on REF pin, PLL disabled unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG BYPASS TO HEADPHONE AMPLIFIER, DIRECT MODE
Device Setup Load = 16Ω (single-ended), 50pF;
Input and Output CM = 0.9V;
Headphone Output on LDOIN Supply;
IN1_L routed to HPL and IN1_R routed to HPR;
Channel Gain = 0dB
Gain Error –0.8 dB
Noise, A-weighted(1) Idle Channel, IN1_L and IN1_R ac-shorted to ground 3 μVRMS
THD Total Harmonic Distortion 446mVrms, 1kHz input signal –89 dB
ANALOG BYPASS TO LINE-OUT AMPLIFIER, PGA MODE
Device Setup Load = 10kΩ (single-ended), 56pF;
Input and Output CM = 0.9V;
LINE Output on LDOIN Supply;
IN1_L routed to ADCPGA_L and IN1_R routed to ADCPGA_R; Rin = 20kΩ
ADCPGA_L routed to LOL and ADCPGA_R routed to LOR; Channel Gain = 0dB
Gain Error 0.6 dB
Noise, A-weighted(1) Idle Channel,
IN1_L and IN1_R ac-shorted to ground		 7 μVRMS
Channel Gain = 40dB,
Input Signal (0dB) = 5mVrms
Inputs ac-shorted to ground, Input Referred		 3.4 μVRMS
(1) All performance measured with 20kHz low-pass filter and, where noted, A-weighted filter. Testing without such a filter may result in higher THD+N and lower SNR and dynamic range readings than shown in the Electrical Characteristics. The low-pass filter removes out-of-band noise, which, although not audible, may affect dynamic specification values.