SLOS602E September   2008  – September 2019 TLV320AIC3204

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Block Diagram
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics, ADC
    6. 7.6  Electrical Characteristics, Bypass Outputs
    7. 7.7  Electrical Characteristics, Microphone Interface
    8. 7.8  Electrical Characteristics, Audio DAC Outputs
    9. 7.9  Electrical Characteristics, LDO
    10. 7.10 Electrical Characteristics, Misc.
    11. 7.11 Electrical Characteristics, Logic Levels
    12. 7.12 I2S LJF and RJF Timing in Master Mode (see )
    13. 7.13 I2S LJF and RJF Timing in Slave Mode (see )
    14. 7.14 DSP Timing in Master Mode (see )
    15. 7.15 DSP Timing in Slave Mode (see )
    16. 7.16 Digital Microphone PDM Timing (see )
    17. 7.17 I2C Interface Timing
    18. 7.18 SPI Interface Timing (See )
    19. 7.19 Typical Characteristics
    20. 7.20 Typical Characteristics, FFT
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Device Connections
        1. 9.3.1.1 Digital Pins
          1. 9.3.1.1.1 Multifunction Pins
        2. 9.3.1.2 Analog Pins
      2. 9.3.2 Analog Audio IO
        1. 9.3.2.1 Analog Low Power Bypass
        2. 9.3.2.2 ADC Bypass Using Mixer Amplifiers
        3. 9.3.2.3 Headphone Outputs
        4. 9.3.2.4 Line Outputs
      3. 9.3.3 ADC
        1. 9.3.3.1 ADC Processing
          1. 9.3.3.1.1 ADC Processing Blocks
      4. 9.3.4 DAC
        1. 9.3.4.1 DAC Processing Blocks
      5. 9.3.5 PowerTune
      6. 9.3.6 Digital Audio IO Interface
      7. 9.3.7 Clock Generation and PLL
      8. 9.3.8 Control Interfaces
        1. 9.3.8.1 I2C Control
        2. 9.3.8.2 SPI Control
    4. 9.4 Device Functional Modes
    5. 9.5 Register Map
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
        1. 10.2.1.1 Reference Filtering Capacitor
        2. 10.2.1.2 MICBIAS
      2. 10.2.2 Detailed Design Procedures
        1. 10.2.2.1 Analog Input Connection
        2. 10.2.2.2 Analog Output Connection
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Community Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.13 I2S LJF and RJF Timing in Slave Mode (see Figure 2)

IOVDD = 1.8V IOVDD = 3.3V UNIT
MIN MAX MIN MAX
tH(BCLK) BCLK high period 35 35 ns
tL(BCLK) BCLK low period 35 35 ns
ts(WS) WCLK setup 8 8 ns
th(WS) WCLK hold 8 8 ns
td(DO-WS) WCLK to DOUT delay (For LJF mode only) 20 20 ns
td(DO-BCLK) BCLK to DOUT delay 22 22 ns
ts(DI) DIN setup 8 8 ns
th(DI) DIN hold 8 8 ns
tr BCLK rise time 4(1) 4(1) ns
tf BCLK fall time 4(1) 4(1) ns
(1) The BCLK maximum rise and fall time can be as high as 10 ns, if the BCLK high and low period are greater than 50 ns.
TLV320AIC3204 i2sljfrlf_los585.gifFigure 2. I2S LJF and RJF Timing in Slave Mode