SLAS538B October   2007  – November 2016 TLV320AIC34

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Hardware Reset
      2. 9.3.2  I2C Bus Debug In A Glitched System
      3. 9.3.3  Digital Audio Data Serial Interface
      4. 9.3.4  TDM Data Transfer
      5. 9.3.5  Audio Data Converters
      6. 9.3.6  Audio Clock Generation
      7. 9.3.7  Stereo Audio ADC
        1. 9.3.7.1 Stereo Audio ADC High-pass Filter
      8. 9.3.8  Digital Audio Processing For Record Path
      9. 9.3.9  Automatic Gain Control (AGC)
      10. 9.3.10 Stereo Audio DAC
      11. 9.3.11 Digital Audio Processing For Playback
      12. 9.3.12 Digital Interpolation Filter
      13. 9.3.13 Delta-Sigma Audio DAC
      14. 9.3.14 Audio DAC Digital Volume Control
      15. 9.3.15 Increasing DAC Dynamic Range
      16. 9.3.16 Analog Output Common-Mode Adjustment
      17. 9.3.17 Audio DAC Power Control
      18. 9.3.18 Audio Analog Inputs
      19. 9.3.19 Analog Input Bypass Path Functionality
      20. 9.3.20 ADC PGA Signal Bypass Path Functionality
      21. 9.3.21 Input Impedance and VCM Control
      22. 9.3.22 Passive Analog Bypass During Power Down
      23. 9.3.23 MICBIAS_x Generation
      24. 9.3.24 Digital Microphone Connectivity
      25. 9.3.25 Analog Fully Differential Line Output Drivers
      26. 9.3.26 Analog High-Power Output Drivers
      27. 9.3.27 Short-Circuit Output Protection
      28. 9.3.28 Jack or Headset Detection
      29. 9.3.29 Output Stage Volume Controls
    4. 9.4 Device Functional Modes
      1. 9.4.1 I2C Control Mode
      2. 9.4.2 Right-Justified Mode
      3. 9.4.3 Left-Justified Mode
      4. 9.4.4 I2S Mode
      5. 9.4.5 DSP Mode
    5. 9.5 Programming
      1. 9.5.1 Digital Control Serial Interface
    6. 9.6 Register Maps
      1. 9.6.1 Register Description
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Related Links
    4. 13.4 Community Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ZAS|87
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

10.1 Application Information

The TLV320AIC34 device is a four-channel, low-power audio codec for portable audio and telephony. It features integrated stereo headphone or line amplifier, as well as multiple inputs and outputs that are programmable in single-ended or fully differential configurations. All the features of the TLV320AIC34 are accessed by programmable registers. External processor with I2C protocol is required to control the device. The protocol is selectable with external pin configuration. It is good practice to perform a hardware reset after initial power up to ensure that all registers are in their default states. Extensive register-based power control is included, enabling stereo 48-KHz DAC playback as low as 15 mW from a 3.3-V analog supply, making it ideal for portable battery-powered audio and telephony applications.

10.2 Typical Application

TLV320AIC34 b0272-01_las538.gif Figure 36. Bluetooth Call Recording Plus Application Audio Block Diagram

10.2.1 Design Requirements

Table 9 lists the design parameters for this application example.

Table 9. Design Parameters

PARAMETER VALUE
Supply voltage (AVDD, DRVDD) 3.3 V
Supply voltage (DVDD, IOVDD) 1.8 V
Analog high-power output driver load 16 Ω
Analog fully differential line output driver load 10 kΩ
Speaker output load resistance (Codec block A only) 8 Ω

10.2.2 Detailed Design Procedure

Using Figure 37 and Figure 38 as guides, integrate the hardware into the system.

TLV320AIC34 s0316-01_las538.gif Figure 37. Typical Connections for TLV320AIC34 in Bluetooth Application (Sheet 1 of 2)
TLV320AIC34 s0317-01_las538.gif Figure 38. Typical Connections for TLV320AIC34 in Bluetooth Application (Sheet 2 of 2)

Following the recommended component placement, schematic layout and routing given in Layout. Integrate the device and its supporting components into the system PCB file. For questions and support, please visit the E2E forums (e2e.ti.com). If it is necessary to deviate from the recommended layout, visit E2E forum to request a layout review.

Determining sample rate and master clock frequency is required, because powering up the device as all internal timing is derived from the master clock. See Audio Clock Generation to get more information of how to configure correctly the required clocks for the device.

As the TLV320AIC34 is designed for low-power applications, when powered up the device has several features powered down. A correct routing of the TLV320AIC34 signals is achieved by a correct setting of the device registers, powering up the required stages of the device and configuring the internal switches to follow a desired route.

In cases where the TDM mode is required, it is necessary to ensure that all the devices take the samples at same time. So, TI recommends the following configuration steps to have all the TDM devices synchronized:

  • Disable the I2S clocks (BCLK, WCLK)
  • Apply a software reset
  • Write the I2C commands for codec configuration (except unmuting the ADCs)
  • Enable the I2S clocks
  • Unmute the ADCs

For more information of the device configuration and programming, see the TLV320AIC34 technical documents section in ti.com (http://www.ti.com/product/TLV320AIC34/technicaldocuments).

10.2.3 Application Curves

TLV320AIC34 thd1_op_las509.gif Figure 39. Total Harmonic Distortion
vs Headphone Out Power
TLV320AIC34 mbias_v_las509.gif Figure 40. MICBIAS_x Voltage vs Supply Voltage