SLAS538B October 2007 – November 2016 TLV320AIC34
PRODUCTION DATA.
Refer to the PDF data sheet for device specific package drawings
MIN | MAX | UNIT | ||
---|---|---|---|---|
DRVDD to AVSS_ADC, AVDD_DAC to AVSS_DAC | –0.3 | 3.9 | V | |
DRVDD to DRVSS | –0.3 | 3.9 | V | |
IOVDD to DVSS | –0.3 | 3.9 | V | |
DVDD to DVSS | –0.3 | 2.5 | V | |
AVDD_DAC to DRVDD | –0.1 | 0.1 | V | |
Digital input voltage to DVSS | –0.3 | IOVDD + 0.3 | V | |
Analog input voltage to AVSS_ADC, AVSS_DAC | –0.3 | AVDD_DAC + 0.3 | V | |
Power dissipation | (TJ Max – TA) / RθJA | |||
Junction temperature, TJ | 105 | °C | ||
Operating temperature, TA | –40 | 85 | °C | |
Storage temperature, Tstg | –65 | 105 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±4000 | V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±1500 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
AVDD_DAC, DRVDD(1) | Analog supply voltage | 2.7 | 3.3 | 3.6 | V |
DVDD(1) | Digital core supply voltage | 1.65 | 1.8 | 1.95 | V |
IOVDD(1) | Digital I/O supply voltage | 1.1 | 1.8 | 3.6 | V |
AVDD_DAC | Analog full-scale 0-dB input voltage (DRVDD = 3.3 V) | 0.707 | VRMS | ||
Stereo line output load resistance (codec block A and codec block B) | 10 | kΩ | |||
Stereo headphone output load resistance (codec block A and codec block B) |
16 | Ω | |||
Stereo speaker output load resistance (codec block A ONLY) | 8 | Ω | |||
Digital output load capacitance | 10 | pF | |||
TA | Operating free-air temperature | –40 | 85 | °C |
THERMAL METRIC(1) | TLV320AIC34 | UNIT | |
---|---|---|---|
ZAS (NFBGA) | |||
87 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 53.8 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 16.3 | °C/W |
RθJB | Junction-to-board thermal resistance | 25.3 | °C/W |
ψJT | Junction-to-top characterization parameter | 3 | °C/W |
ψJB | Junction-to-board characterization parameter | 26.4 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
AUDIO ADC – CODEC BLOCK A, B | |||||||
Input signal level (0-dB) | Single-ended input | 0.707 | VRMS | ||||
SNR | Signal-to-noise ratio(1)(2) | fS = 48 ksps, 0-dB PGA gain, LINE1LP_x and LINE1LM_x inputs ac-shorted to ground, A-weighted | 80 | 92 | dB | ||
Dynamic range(2) | fS = 48 ksps, 0-dB PGA gain, –60-dB full-scale input signal applied at LINE1LP_x and LINE1LM_x inputs, A-weighted | 93 | dB | ||||
THD | Total harmonic distortion | fS = 48 ksps, 0-dB PGA gain, –2-dB full-scale 1-kHz input signal applied at LINE1LP_x and LINE1LM_x inputs | –87 | –70 | dB | ||
PSRR | Power supply rejection ratio | 217-Hz signal applied to DRVDD | 49 | dB | |||
1-kHz signal applied to DRVDD | 46 | ||||||
Gain error | fS = 48 ksps, 0-dB PGA gain, –2-dB full-scale 1-kHz input signal applied on LINE1LP_x and LINE1LM_x inputs | 0.55 | dB | ||||
Input channel separation | 1-kHz, –2-dB full-scale signal, MIC3L_x to MIC3R_x | –86 | dB | ||||
1-kHz, –2-dB full-scale signal, MIC2LP_x and MIC2LM_x to MIC2RP_x and MIC2RM_x | –98 | ||||||
1-kHz, –2-dB full-scale signal, MIC1LP_x and MIC1LM_x to MIC1RP_x and MIC1RM_x | –80 | ||||||
ADC programmable-gain amplifier maximum gain | 1-kHz input frequency, RSOURCE < 50 Ω | 59.5 | dB | ||||
ADC programmable-gain amplifier step size | 1-kHz input frequency, RSOURCE < 50 Ω | 0.5 | dB | ||||
Input resistance | LINE1LP_x, LINE1LM_x, or LINE1RP_x, LINE1RM_x inputs routed to single ADC; input mix attenuation = 0 dB |
20 | kΩ | ||||
LINE1LP_x, LINE1LM_x, or LINE1RP_x, LINE1RM_x inputs routed to single ADC; input mix attenuation = 12 dB | 80 | ||||||
LINE2LP_x, LINE2LM_x, or LINE2RP_x, LINE2RM_x inputs routed to single ADC; input mix attenuation = 0 dB |
20 | ||||||
LINE2LP_x, LINE2LM_x, or LINE2RP_x, LINE2RM_x inputs routed to single ADC; input mix attenuation = 12 dB | 80 | ||||||
MIC3L_x or MIC3R_x inputs routed to single ADC, input mix attenuation = 0 dB |
20 | ||||||
MIC3L_x or MIC3R_x inputs routed to single ADC, input mix attenuation = 12 dB | 80 | ||||||
Input level control minimum attenuation setting | 0 | dB | |||||
Input level control maximum attenuation setting | 12 | dB | |||||
Input signal level | Differential input | 1.414 | VRMS | ||||
SNR | Signal-to-noise ratio(1)(2) | fS = 48 ksps, 0-dB PGA gain, inputs ac-shorted to ground, differential mode, A-weighted | 92 | dB | |||
THD | Total harmonic distortion | fS = 48 ksps, 0-dB PGA gain, –2-dB full-scale 1-kHz input signal, differential mode, A-weighted | –89 | dB | |||
ANALOG PASS-THROUGH MODE – CODEC BLOCK A, B | |||||||
rds(on) | Input-to-output switch resistance | MIC1/LINE1 to LINE_OUT | 330 | Ω | |||
MIC2/LINE2 to LINE_OUT | 330 | ||||||
ADC DIGITAL DECIMATION FILTER, fS = 48 kHz – CODEC BLOCK A, B | |||||||
Filter gain from 0 to 0.39 fS | ±0.1 | dB | |||||
Filter gain at 0.4125 fS | –0.25 | dB | |||||
Filter gain at 0.45 fS | –3 | dB | |||||
Filter gain at 0.5 fS | –17.5 | dB | |||||
Filter gain from 0.55 fS to 64 fS | –75 | dB | |||||
Filter group delay | 17/fS | s | |||||
MICROPHONE BIAS – CODEC BLOCK A, B | |||||||
Bias voltage | Programmable setting = 2 V, load current = 4 mA | 2 | V | ||||
Programmable setting = 2.5 V, load current = 4 mA | 2.3 | 2.4 | 2.7 | ||||
Programmable setting = DRVDD (3.3 V), load current = 4 mA | 3 | ||||||
Current sourcing | Programmable setting = 2.5 V | 4 | mA | ||||
AUDIO DAC – DIFFERENTIAL LINE OUTPUT, LOAD = 10 kΩ – CODEC BLOCK A, B | |||||||
Full-scale output voltage | 0-dB input full-scale signal, output volume control = 0 dB, output common-mode setting = 1.35 V | 1.414 | VRMS | ||||
SNR | Signal-to-noise ratio(3) | No input signal, output volume control = 0 dB, output common-mode setting = 1.35 V, fS = 48 kHz, A-weighted | 90 | 99 | dB | ||
Dynamic range | –60 dB, 1-kHz input full-scale signal, output volume control = 0 dB, output common-mode setting = 1.35 V, fS = 48 kHz, A-weighted | 95 | dB | ||||
THD | Total harmonic distortion | 0-dB, 1-kHz input full-scale signal, output volume control = 0 dB, output common-mode setting = 1.35 V, fS = 48 kHz | –88 | –75 | dB | ||
PSRR | Power-supply rejection ratio | 217-Hz signal applied to AVDD_DAC | 77 | dB | |||
1-kHz signal applied to AVDD_DAC | 73 | ||||||
DAC channel separation | 0-dB full-scale input signal between left and right lineout | 123 | dB | ||||
DAC gain error | 0-dB, 1-kHz input full-scale signal, output volume control = 0 dB, output common-mode setting = 1.35 V, fS = 48 kHz | –0.49 | dB | ||||
AUDIO DAC – SINGLE-ENDED LINE OUTPUT, LOAD = 10 kΩ – CODEC BLOCK A, B | |||||||
Full-scale output voltage | 0-dB input full-scale signal, output volume control = 0 dB, output common-mode setting = 1.35 V | 0.707 | Vrms | ||||
SNR | Signal-to-noise ratio | No input signal, output volume control = 0 dB, output common-mode setting = 1.35 V, fS = 48 kHz, A-weighted | 94 | dB | |||
THD | Total harmonic distortion | 0-dB, 1-kHz input full-scale signal, output volume control = 0 dB, output common-mode setting = 1.35 V, fS = 48 kHz | 79 | dB | |||
DAC gain error | 0-dB, 1-kHz input full-scale signal, output volume control = 0 dB, output common-mode setting = 1.35 V, fS = 48 kHz | –0.5 | dB | ||||
AUDIO DAC – SINGLE-ENDED HEADPHONE OUTPUT, LOAD = 16 Ω – CODEC BLOCK A, B | |||||||
Full-scale output voltage | 0-dB input full-scale signal, output volume control = 0 dB, output common-mode setting = 1.35 V | 0.707 | Vrms | ||||
SNR | Signal-to-noise ratio | No input signal, output volume control = 0 dB, output common-mode setting = 1.35 V, fS = 48 kHz, A-weighted | 93 | dB | |||
No input signal, output volume control = 0 dB, output common-mode setting = 1.35 V, fS = 48 kHz, 50% DAC current boost, A-weighted | 94 | dB | |||||
Dynamic range | –60 dB, 1-kHz input full-scale signal, output volume control = 0 dB, output common-mode setting = 1.35 V, fS = 48 kHz, A-weighted | 89 | dB | ||||
THD | Total harmonic distortion | 0-dB, 1-kHz input full-scale signal, output volume control = 0 dB, output common-mode setting = 1.35 V, fS = 48 kHz | –74 | –65 | dB | ||
PSRR | Power-supply rejection ratio | 217-Hz signal applied to DRVDD, AVDD_DAC | 41 | dB | |||
1-kHz signal applied to DRVDD, AVDD_DAC | 44 | ||||||
DAC channel separation | 0-dB full-scale input signal between left and right headphone out | 84 | dB | ||||
DAC gain error | 0-dB, 1-kHz input full-scale signal, output volume control = 0 dB, output common-mode setting = 1.35 V, fS = 48 kHz | –0.8 | dB | ||||
AUDIO DAC – LINEOUT AND HEADPHONE OUT DRIVERS – CODEC BLOCK A, B | |||||||
Output common mode | First option | 1.35 | V | ||||
Second option | 1.5 | ||||||
Third option | 1.65 | ||||||
Fourth option | 1.8 | ||||||
Output volume-control maximum setting | 9 | dB | |||||
Output volume-control step size | 1 | dB | |||||
AUDIO DAC – DIFFERENTIAL SPEAKER OUTPUT, RLOAD = 8 Ω, 1 kHz INPUT SIGNAL – CODEC BLOCK A ONLY | |||||||
Full-scale output voltage, codec block A only | 0-dB input full-scale signal, output common-mode setting = 1.35 V, output volume control = 0 dB | 1.414 | VRMS | ||||
SNR | Signal-to-noise ratio, codec block A only | A-weighted, fS = 48 kHz, output volume control = 0 dB, no input signal, output common-mode setting = 1.35 V | 96 | dB | |||
THD | Total harmonic distortion, codec block A only | fS = 48 kHz, 1-kHz input full-scale signal, output volume control = 0 dB, output common-mode setting = 1.35 V | –67 | dB | |||
DAC gain error, codec block A only | fS = 48 kHz, 1-kHz input full-scale signal, output volume control = 0 dB, output common-mode setting = 1.35 V | –2 | dB | ||||
DAC DIGITAL INTERPOLATION, FILTER fS = 48-ksps – CODEC BLOCK A, B | |||||||
Pass band | 0 | 0.45 fS | Hz | ||||
Pass-band ripple | ±0.06 | dB | |||||
Transition band | 0.45 fS | 0.55 fS | Hz | ||||
Stop band | 0.55 fS | 7.5 fS | Hz | ||||
Stop-band attenuation | 65 | dB | |||||
Group delay | 21 / fS | s | |||||
DIGITAL I/O – CODEC BLOCK A, B | |||||||
VIL | Input low level | –0.3 | 0.3 IOVDD | V | |||
VIH | Input high level(4) | IOVDD > 1.6 V | 0.7 IOVDD | V | |||
IOVDD < 1.6 V | 1.1 | ||||||
VOL | Output low level | 0.1 IOVDD | V | ||||
VOH | Output high level | 0.8 IOVDD | V | ||||
POWER CONSUMPTION, DRVDD, AVDD_DAC = 3.3 V, DVDD = 1.8 V, IOVDD = 3.3 V – CURRENTS LISTED FOR CODEC BLOCK A OR BLOCK B | |||||||
IIN | IDRVDD + IAVDD_DAC | RESET_x pulse applied, no external clocks | 1.19 | µA | |||
IDVDD | RESET_x pulse applied, no external clocks | 0.75 | |||||
IDRVDD + IAVDD_DAC | Mono ADC record, fS = 8 ksps, I2S slave, AGC off, no signal, PLL off | 2.06 | mA | ||||
IDVDD | Mono ADC record, fS = 8 ksps, I2S slave, AGC off, no signal, PLL off | 0.55 | |||||
IDRVDD + IAVDD_DAC | Stereo ADC record, fS = 8 ksps, I2S slave, AGC off, no signal, PLL off | 4.06 | |||||
IDVDD | Stereo ADC record, fS = 8 ksps, I2S slave, AGC off, no signal, PLL off | 0.67 | |||||
IDRVDD + IAVDD_DAC | Stereo ADC record, fS = 48 ksps, I2S slave, AGC off, no signal, PLL off | 4.27 | |||||
IDVDD | Stereo ADC record, fS = 48 ksps, I2S slave, AGC off, no signal, PLL off | 2.45 | |||||
IDRVDD + IAVDD_DAC | Stereo DAC playback to lineout, analog mixer bypassed, fS = 48 ksps, I2S slave, no signal, PLL off | 3.5 | |||||
IDVDD | Stereo DAC playback to lineout, analog mixer bypassed, fS = 48 ksps, I2S slave, no signal, PLL off | 2.3 | |||||
IDRVDD + IAVDD_DAC | Stereo DAC playback to Lineout, fS = 48 ksps, I2S slave, no signal, PLL off | 4.42 | |||||
IDVDD | Stereo DAC playback to Lineout, fS = 48 ksps, I2S slave, no signal, PLL off | 2.27 | |||||
IDRVDD + IAVDD_DAC | Stereo DAC playback to stereo single-ended headphones, fS = 48 ksps, I2S slave, no signal, PLL off | 7.78 | |||||
IDVDD | Stereo DAC playback to stereo single-ended headphones, fS = 48 ksps, I2S slave, no signal, PLL off | 2.26 | |||||
IDRVDD + IAVDD_DAC | Stereo linein to stereo lineout, no signal | 3.16 | |||||
IDVDD | Stereo linein to stereo lineout, no signal | 1.79 | |||||
IDRVDD + IAVDD_DAC | Extra power when PLL enabled | 1.2 | |||||
IDVDD | Extra power when PLL enabled | 1 | |||||
IDRVDD + IAVDD_DAC | All blocks powered down, headset detection enabled | 5.3 | µA | ||||
IDVDD | All blocks powered down, headset detection enabled | 188 |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
I2S, LJF, RJF TIMING IN MASTER MODE (SEE Figure 1) | ||||||
td(WS) | ADWS/WCLK_x delay time | IOVDD = 1.1 V | 50 | ns | ||
IOVDD = 3.3 V | 15 | |||||
td(DO-WS) | ADWS/WCLK_x to DOUT_x delay time | IOVDD = 1.1 V | 50 | ns | ||
IOVDD = 3.3 V | 20 | |||||
td(DO-BCLK) | BCLK_x to DOUT_x delay time | IOVDD = 1.1 V | 50 | ns | ||
IOVDD = 3.3 V | 15 | |||||
ts(DI) | DIN_x setup time | IOVDD = 1.1 V | 10 | ns | ||
IOVDD = 3.3 V | 6 | |||||
th(DI) | DIN_x hold time | IOVDD = 1.1 V | 10 | ns | ||
IOVDD = 3.3 V | 6 | |||||
tr | Rise time | IOVDD = 1.1 V | 30 | ns | ||
IOVDD = 3.3 V | 10 | |||||
tf | Fall time | IOVDD = 1.1 V | 30 | ns | ||
IOVDD = 3.3 V | 10 | |||||
DSP TIMING IN MASTER MODE (SEE Figure 2) | ||||||
td(WS) | ADWS/WCLK_x delay time | IOVDD = 1.1 V | 50 | ns | ||
IOVDD = 3.3 V | 15 | |||||
td(DO-BCLK) | BCLK_x to DOUT_x delay time | IOVDD = 1.1 V | 50 | ns | ||
IOVDD = 3.3 V | 15 | |||||
ts(DI) | DIN_x setup time | IOVDD = 1.1 V | 10 | ns | ||
IOVDD = 3.3 V | 6 | |||||
th(DI) | DIN_x hold time | IOVDD = 1.1 V | 10 | ns | ||
IOVDD = 3.3 V | 6 | |||||
tr | Rise time | IOVDD = 1.1 V | 30 | ns | ||
IOVDD = 3.3 V | 10 | |||||
tf | Fall time | IOVDD = 1.1 V | 30 | ns | ||
IOVDD = 3.3 V | 10 | |||||
I2S, LJF, RJF TIMING IN SLAVE MODE (SEE Figure 3) | ||||||
tH(BCLK) | BCLK_x high period | IOVDD = 1.1 V | 70 | ns | ||
IOVDD = 3.3 V | 35 | |||||
tL(BCLK) | BCLK_x low period | IOVDD = 1.1 V | 70 | ns | ||
IOVDD = 3.3 V | 35 | |||||
ts(WS) | ADWS/WCLK_x setup time | IOVDD = 1.1 V | 10 | ns | ||
IOVDD = 3.3 V | 6 | |||||
th(WS) | ADWS/WCLK_x hold time | IOVDD = 1.1 V | 10 | ns | ||
IOVDD = 3.3 V | 6 | |||||
td(DO-WS) | ADWS/WCLK_x to DOUT_x delay time (for LJF mode only) |
IOVDD = 1.1 V | 50 | ns | ||
IOVDD = 3.3 V | 20 | |||||
td(DO-BCLK) | BCLK_x to DOUT_x delay time | IOVDD = 1.1 V | 50 | ns | ||
IOVDD = 3.3 V | 20 | |||||
ts(DI) | DIN_x setup time | IOVDD = 1.1 V | 10 | ns | ||
IOVDD = 3.3 V | 6 | |||||
th(DI) | DIN_x hold time | IOVDD = 1.1 V | 10 | ns | ||
IOVDD = 3.3 V | 6 | |||||
tr | Rise time | IOVDD = 1.1 V | 8 | ns | ||
IOVDD = 3.3 V | 4 | |||||
tf | Fall time | IOVDD = 1.1 V | 8 | ns | ||
IOVDD = 3.3 V | 4 | |||||
DSP TIMING IN SLAVE MODE (SEE Figure 4) | ||||||
tH(BCLK) | BCLK_x high period | IOVDD = 1.1 V | 70 | ns | ||
IOVDD = 3.3 V | 35 | |||||
tL(BCLK) | BCLK_x low period | IOVDD = 1.1 V | 70 | ns | ||
IOVDD = 3.3 V | 35 | |||||
ts(WS) | ADWS/WCLK_x setup time | IOVDD = 1.1 V | 10 | ns | ||
IOVDD = 3.3 V | 6 | |||||
th(WS) | ADWS/WCLK_x hold time | IOVDD = 1.1 V | 10 | ns | ||
IOVDD = 3.3 V | 6 | |||||
td(DO-BCLK) | BCLK_x to DOUT_x delay time | IOVDD = 1.1 V | 50 | ns | ||
IOVDD = 3.3 V | 20 | |||||
ts(DI) | DIN_x setup time | IOVDD = 1.1 V | 10 | ns | ||
IOVDD = 3.3 V | 6 | |||||
th(DI) | DIN_x hold time | IOVDD = 1.1 V | 10 | ns | ||
IOVDD = 3.3 V | 6 | |||||
tr | Rise time | IOVDD = 1.1 V | 6 | ns | ||
IOVDD = 3.3 V | 4 | |||||
tf | Fall time | IOVDD = 1.1 V | 6 | ns | ||
IOVDD = 3.3 V | 4 |