SLAS666B January 2010 – October 2018 TLV320DAC3101
PRODUCTION DATA.
BIT | READ/
WRITE |
RESET
VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | 0000 0000 | 0000 0000: Page 0 selected
0000 0001: Page 1 selected ... 1111 1110: Page 254 selected 1111 1111: Page 255 selected |
BIT | READ/
WRITE |
RESET
VALUE |
DESCRIPTION |
---|---|---|---|
D7–D1 | R/W | 0000 000 | Reserved. Write only zeros to these bits. |
D0 | R/W | 0 | 0: Don't care
1: Self-clearing software reset for control register |
BIT | READ/
WRITE |
RESET
VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R | XXXX XXXX | Reserved. Do not write to this register. |
BIT | READ/
WRITE |
RESET
VALUE |
DESCRIPTION |
---|---|---|---|
D7-D2 | R | XXXX XX | Reserved. Do not write to these bits. |
D1 | R | 1 | 0: Overtemperature protection flag (active-low). Valid only if speaker amplifier is powered up
1: Normal operation |
D0 | R/W | X | Reserved. Do not write to these bits. |
BIT | READ/
WRITE |
RESET
VALUE |
DESCRIPTION |
---|---|---|---|
D7–D4 | R/W | 0000 | Reserved. Write only zeros to these bits. |
D3–D2 | R/W | 00 | 00: PLL_CLKIN = MCLK (device pin)
01: PLL_CLKIN = BCLK (device pin) 10: PLL_CLKIN = GPIO1 (device pin) 11: PLL_CLKIN = DIN (can be used for the system where DAC is not used) |
D1–D0 | R/W | 00 | 00: CODEC_CLKIN = MCLK (device pin)
01: CODEC_CLKIN = BCLK (device pin) 10: CODEC_CLKIN = GPIO1 (device pin) 11: CODEC_CLKIN = PLL_CLK (generated on-chip) |
BIT | READ/
WRITE |
RESET
VALUE |
DESCRIPTION |
---|---|---|---|
D7 | R/W | 0 | 0: PLL is powered down.
1: PLL is powered up. |
D6–D4 | R/W | 001 | 000: PLL divider P = 8
001: PLL divider P = 1 010: PLL divider P = 2 ... 110: PLL divider P = 6 111: PLL divider P = 7 |
D3–D0 | R/W | 0001 | 0000: PLL multiplier R = 16
0001: PLL multiplier R = 1 0010: PLL multiplier R = 2 ... 1110: PLL multiplier R = 14 1111: PLL multiplier R = 15 |
BIT | READ/
WRITE |
RESET
VALUE |
DESCRIPTION |
---|---|---|---|
D7–D6 | R/W | 00 | Reserved. Write only zeros to these bits. |
D5–D0 | R/W | 00 0100 | 00 0000: Do not use (reserved)
00 0001: PLL multiplier J = 1 00 0010: PLL multiplier J = 2 ... 11 1110: PLL multiplier J = 62 11 1111: PLL multiplier J = 63 |
BIT | READ/
WRITE |
RESET
VALUE |
DESCRIPTION |
---|---|---|---|
D7–D6 | R/W | 00 | Reserved. Write only zeros to these bits. |
D5–D0 | R/W | 00 0000 | PLL fractional multiplier D-value MSB bits D[13:8] |
BIT | READ/
WRITE |
RESET
VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | 0000 0000 | PLL fractional multiplier D-value LSB bits D[7:0] |
BIT | READ/
WRITE |
RESET
VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R | XXXX XXXX | Reserved. |
BIT | READ/
WRITE |
RESET
VALUE |
DESCRIPTION |
---|---|---|---|
D7 | R/W | 0 | 0: DAC NDAC divider is powered down.
1: DAC NDAC divider is powered up. |
D6–D0 | R/W | 000 0001 | 000 0000: DAC NDAC divider = 128
000 0001: DAC NDAC divider = 1 000 0010: DAC NDAC divider = 2 ... 111 1110: DAC NDAC divider = 126 111 1111: DAC NDAC divider = 127 |
BIT | READ/
WRITE |
RESET
VALUE |
DESCRIPTION |
---|---|---|---|
D7 | R/W | 0 | 0: DAC MDAC divider is powered down.
1: DAC MDAC divider is powered up. |
D6–D0 | R/W | 000 0001 | 000 0000: DAC MDAC divider = 128
000 0001: DAC MDAC divider = 1 000 0010: DAC MDAC divider = 2 ... 111 1110: DAC MDAC divider = 126 111 1111: DAC MDAC divider = 127 |
BIT | READ/
WRITE |
RESET
VALUE |
DESCRIPTION |
---|---|---|---|
D7–D2 | R/W | 0000 00 | Reserved |
D1–D0 | R/W | 00 | DAC OSR value DOSR(9:8) |
BIT | READ/
WRITE |
RESET
VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | XXXX XXXX | Reserved. Do not write to these registers. |
BIT | READ/
WRITE |
RESET
VALUE |
DESCRIPTION |
---|---|---|---|
D7–D3 | R/W | 0000 0 | Reserved |
D2–D0 | R/W | 000 | 000: CDIV_CLKIN = MCLK (device pin)
001: CDIV_CLKIN = BCLK (device pin) 010: CDIV_CLKIN = DIN (can be used for the systems where DAC is not required) 011: CDIV_CLKIN = PLL_CLK (generated on-chip) 100: CDIV_CLKIN = DAC_CLK (DAC DSP clock - generated on-chip) 101: CDIV_CLKIN = DAC_MOD_CLK (generated on-chip) 110: Reserved 111: Reserved |
BIT | READ/
WRITE |
RESET
VALUE |
DESCRIPTION |
---|---|---|---|
D7 | R/W | 0 | 0: CLKOUT M divider is powered down.
1: CLKOUT M divider is powered up. |
D6–D0 | R/W | 000 0001 | 000 0000: CLKOUT divider M = 128
000 0001: CLKOUT divider M = 1 000 0010: CLKOUT divider M = 2 ... 111 1110: CLKOUT divider M = 126 111 1111: CLKOUT divider M = 127 |
BIT | READ/
WRITE |
RESET
VALUE |
DESCRIPTION |
---|---|---|---|
D7–D6 | R/W | 00 | 00: Codec interface = I2S
01: Codec Interface = DSP 10: Codec interface = RJF 11: Codec interface = LJF |
D5–D4 | R/W | 00 | 00: Codec interface word length = 16 bits
01: Codec interface word length = 20 bits 10: Codec interface word length = 24 bits 11: Codec interface word length = 32 bits |
D3 | R/W | 0 | 0: BCLK is input
1: BCLK is output |
D2 | R/W | 0 | 0: WCLK is input
1: WCLK is output |
D1–D0 | R/W | 0 | Reserved |
BIT | READ/
WRITE |
RESET
VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | 0000 0000 | Offset (Measured With Respect to WCLK Rising Edge in DSP Mode)
0000 0000: Offset = 0 BCLKs 0000 0001: Offset = 1 BCLK 0000 0010: Offset = 2 BCLKs ... 1111 1110: Offset = 254 BCLKs 1111 1111: Offset = 255 BCLKs |
BIT | READ/
WRITE |
RESET
VALUE |
DESCRIPTION |
---|---|---|---|
D7–D4 | R/W | 0000 | Reserved |
D3 | R/W | 0 | 0: BCLK is not inverted (valid for both primary and secondary BCLK)
1: BCLK is inverted (valid for both primary and secondary BCLK) |
D2 | R/W | 0 | BCLK and WCLK Active Even With Codec Powered Down (Valid for Both Primary and Secondary BCLK)
0: Disabled 1: Enabled |
D1–D0 | R/W | 00 | 00: BDIV_CLKIN = DAC_CLK (generated on-chip)
01: BDIV_CLKIN = DAC_MOD_CLK (generated on-chip) 10: Reserved 11: Reserved |
BIT | READ/
WRITE |
RESET
VALUE |
DESCRIPTION |
---|---|---|---|
D7 | R/W | 0 | 0: BCLK N-divider is powered down.
1: BCLK N-divider is powered up. |
D6–D0 | R/W | 000 0001 | 000 0000: BCLK divider N = 128
000 0001: BCLK divider N = 1 000 0010: BCLK divider N = 2 ... 111 1110: BCLK divider N = 126 111 1111: BCLK divider N = 127 |
BIT | READ/
WRITE |
RESET
VALUE |
DESCRIPTION |
---|---|---|---|
D7–D5 | R/W | 000 | 000: Secondary BCLK is obtained from GPIO1 pin.
001: Secondary BCLK is not obtained from the GPIO1 pin. 010: Reserved. 011: Reserved. 100: Reserved 101: Reserved. 110: Reserved. 111: Reserved |
D4–D2 | R/W | 000 | 000: Secondary WCLK is obtained from GPIO1 pin.
001: Secondary WCLK is not obtained from the GPIO1 pin. 010: Reserved. 011: Reserved. 100: Reserved 101: Reserved. 110: Reserved. 111: Reserved |
D1–D0 | R/W | 00 | 00: Secondary DIN is obtained from the GPIO1 pin.
01: Secondary DIN is not obtained from the GPIO1 pin. 10: Reserved. 10–11: Reserved |
BIT | READ/
WRITE |
RESET
VALUE |
DESCRIPTION |
---|---|---|---|
D7–D4 | R/W | 0000 | Reserved |
D3 | R/W | 0 | 0: Primary BCLK is fed to codec serial-interface and ClockGen blocks.
1: Secondary BCLK is fed to codec serial-interface and ClockGen blocks. |
D2 | R/W | 0 | 0: Primary WCLK is fed to codec serial-interface block.
1: Secondary WCLK is fed to codec serial-interface block. |
D1 | R/W | 0 | Reserved. |
D0 | R/W | 0 | 0: Primary DIN is fed to codec serial-interface block.
1: Secondary DIN is fed to codec serial-interface block. |
BIT | READ/
WRITE |
RESET
VALUE |
DESCRIPTION |
---|---|---|---|
D7 | R/W | 0 | 0: Primary BCLK output = internally generated BCLK clock
1: Primary BCLK output = secondary BCLK |
D6 | R/W | 0 | 0: Secondary BCLK output = primary BCLK
1: Secondary BCLK output = internally generated BCLK clock |
D5–D4 | R/W | 00 | 00: Primary WCLK output = internally generated DAC_fS
01: Reserved 10: Primary WCLK output = secondary WCLK 11: Reserved |
D3–D2 | R/W | 00 | 00: Secondary WCLK output = primary WCLK
01: Secondary WCLK output = internally generated DAC_fS clock 10: Reserved 11: Reserved |
D1–D0 | R/W | 0 | Reserved |
BIT | READ/
WRITE |
RESET
VALUE |
DESCRIPTION |
---|---|---|---|
D7–D6 | R/W | 00 | Reserved. Write only the reset value to these bits. |
D5 | R/W | 0 | 0: I2C general-call address is ignored.
1: Device accepts I2C general-call address. |
D4–D0 | R/W | 0 0000 | Reserved. Write only zeros to these bits. |
BIT | READ/
WRITE |
RESET
VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | XXXX XXXX | Reserved. Write only zeros to these bits. |
BIT | READ/
WRITE |
RESET
VALUE |
DESCRIPTION |
---|---|---|---|
D7 | R | 0 | 0: Left-channel DAC powered down
1: Left-channel DAC powered up |
D6 | R/W | X | Reserved. Write only zero to this bit. |
D5 | R | 0 | 0: HPL driver powered down
1: HPL driver powered up |
D4 | R | 0 | 0: Left-channel class-D driver powered down
1: Left-channel class-D driver powered up |
D3 | R | 0 | 0: Right-channel DAC powered down
1: Right-channel DAC powered up |
D2 | R/W | X | Reserved. Write only zero to this bit. |
D1 | R | 0 | 0: HPR driver powered down
1: HPR driver powered up |
D0 | R | 0 | 0: Right-channel class-D driver powered down
1: Right-channel class-D driver powered up |
BIT | READ/
WRITE |
RESET
VALUE |
DESCRIPTION |
---|---|---|---|
D7–D5 | R/W | XXX | Reserved. Do not write to these bits. |
D4 | R | 0 | 0: Left-channel DAC PGA applied gain ≠ programmed gain
1: Left-channel DAC PGA applied gain = programmed gain |
D3–D1 | R/W | XXX | Reserved. Write only zeros to these bits. |
D0 | R | 0 | 0: Right-channel DAC PGA applied gain ≠ programmed gain
1: Right-channel DAC PGA applied gain = programmed gain |
BIT | READ/
WRITE |
RESET
VALUE |
DESCRIPTION |
---|---|---|---|
D7(1) | R | 0 | Left-Channel DAC Overflow Flag
0: Overflow has not occurred. 1: Overflow has occurred. |
D6(1) | R | 0 | Right-Channel DAC Overflow Flag
0: Overflow has not occurred. 1: Overflow has occurred. |
D5(1) | R | 0 | DAC Barrel Shifter Output Overflow Flag
0: Overflow has not occurred. 1: Overflow has occurred. |
D4–D0 | R | 0 | Reserved. |
BIT | READ/
WRITE |
RESET
VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | XXXX XXXX | Reserved. Write only the reset value to these bits. |
BIT | READ/
WRITE |
RESET
VALUE |
DESCRIPTION |
---|---|---|---|
D7(1) | R | 0 | 0: No short circuit is detected at HPL / left class-D driver.
1: Short circuit is detected at HPL / left class-D driver. |
D6(1) | R | 0 | 0: No short circuit is detected at HPR / right class-D driver.
1: Short circuit is detected at HPR / right class-D driver. |
D5(1) | R | X | 0: No headset button pressed.
1: Headset button pressed. |
D4(1) | R | X | 0: No headset insertion or removal is detected.
1: Headset insertion or removal is detected. |
D3(1) | R | 0 | 0: Left DAC signal power is less than or equal to the signal threshold of DRC.
1: Left DAC signal power is above the signal threshold of DRC. |
D2(1) | R | 0 | 0: Right DAC signal power is less than or equal to the signal threshold of DRC.
1: Right DAC signal power is above the signal threshold of DRC. |
D1-D0 | R | 0 | Reserved. |
BIT | READ/
WRITE |
RESET
VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | XXXX XXXX | Reserved. Write only zeros to these bits. |
BIT | READ/
WRITE |
RESET
VALUE |
DESCRIPTION |
---|---|---|---|
D7 | R | 0 | 0: No short circuit detected at HPL / left class-D driver.
1: Short circuit detected at HPL / left class-D driver. |
D6 | R | 0 | 0: No short circuit detected at HPR / right class-D driver
1: Short circuit detected at HPR / right class-D driver |
D5 | R | X | 0: No headset button pressed.
1: Headset button pressed. |
D4 | R | X | 0: Headset removal detected.
1: Headset insertion detected. |
D3 | R | 0 | 0: Left DAC signal power is less than or equal to signal threshold of DRC.
1: Left DAC signal power is greater than signal threshold of DRC. |
D2 | R | 0 | 0: Right DAC signal power is less than or equal to signal threshold of DRC.
1: Right DAC signal power is greater than signal threshold of DRC. |
D1–D0 | R | 00 | Reserved. |
BIT | READ/
WRITE |
RESET
VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R | 0000 0000 | Reserved. |
BIT | READ/
WRITE |
RESET
VALUE |
DESCRIPTION |
---|---|---|---|
D7 | R/W | 0 | 0: Headset-insertion detect interrupt is not used in the generation of INT1 interrupt.
1: Headset-insertion detect interrupt is used in the generation of INT1 interrupt. |
D6 | R/W | 0 | 0: Button-press detect interrupt is not used in the generation of INT1 interrupt.
1: Button-press detect interrupt is used in the generation of INT1 interrupt. |
D5 | R/W | 0 | 0: DAC DRC signal-power interrupt is not used in the generation of INT1 interrupt.
1: DAC DRC signal-power interrupt is used in the generation of INT1 interrupt. |
D4 | R/W | 0 | Reserved |
D3 | R/W | 0 | 0: Short-circuit interrupt is not used in the generation of INT1 interrupt.
1: Short-circuit interrupt is used in the generation of INT1 interrupt. |
D2 | R/W | 0 | 0: DAC data overflow does not result in an INT1 interrupt.
1: DAC data overflow results in an INT1 interrupt. |
D1 | R/W | 0 | Reserved |
D0 | R/W | 0 | 0: INT1 is only one pulse (active-high) of typical 2-ms duration.
1: INT1 is multiple pulses (active-high) of typical 2-ms duration and 4-ms period, until flag register 44 is read by the user. |
BIT | READ/
WRITE |
RESET
VALUE |
DESCRIPTION |
---|---|---|---|
D7 | R/W | 0 | 0: Headset-insertion detect interrupt is not used in the generation of INT2 interrupt.
1: Headset-insertion detect interrupt is used in the generation of INT2 interrupt. |
D6 | R/W | 0 | 0: Button-press detect interrupt is not used in the generation of INT2 interrupt.
1: Button-press detect interrupt is used in the generation of INT2 interrupt. |
D5 | R/W | 0 | 0: DAC DRC signal-power interrupt is not used in the generation of INT2 interrupt.
1: DAC DRC signal-power interrupt is used in the generation of INT2 interrupt. |
D4 | R/W | 0 | Reserved |
D3 | R/W | 0 | 0: Short-circuit interrupt is not used in the generation of INT2 interrupt.
1: Short-circuit interrupt is used in the generation of INT2 interrupt. |
D2 | R/W | 0 | 0: DAC data overflow does not result in an INT2 interrupt.
1: DAC data overflow results in an INT2 interrupt. |
D1 | R/W | 0 | Reserved |
D0 | R/W | 0 | 0: INT2 is only one pulse (active-high) of typical 2-ms duration.
1: INT2 is multiple pulses (active-high) of typical 2-ms duration and 4-ms period, until flag register 44is read by the user. |
BIT | READ/
WRITE |
RESET
VALUE |
DESCRIPTION |
---|---|---|---|
D7-D0 | R/W | 0000 0000 | Reserved. Write only reset values. |
BIT | READ/
WRITE |
RESET
VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | XXXX XXXX | Reserved. Do not write any value other than reset value. |
BIT | READ/
WRITE |
RESET
VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R | 0000 0000 | Reserved |
BIT | READ/
WRITE |
RESET
VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R | XXXX XXXX | Reserved. Do not write to these registers. |
BIT | READ/
WRITE |
RESET
VALUE |
DESCRIPTION |
---|---|---|---|
D7–D5 | R/W | 000 | Reserved. Write only default value. |
D4–D0 | R/W | 00 0001 | 0 0000: Reserved. Do not use.
0 0001: DAC signal-processing block PRB_P1 0 0010: DAC signal-processing block PRB_P2 0 0011: DAC signal-processing block PRB_P3 0 0100: DAC signal-processing block PRB_P4 ... 1 1000: DAC signal-processing block PRB_P24 1 1001: DAC signal-processing block PRB_P25 1 1010–1 1111: Reserved. Do not use. |
BIT | READ/
WRITE |
RESET
VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R | XXXX XXXX | Reserved. Do not write. |
BIT | READ/
WRITE |
RESET
VALUE |
DESCRIPTION |
---|---|---|---|
D7 | R/W | 0 | 0: Left-channel DAC is powered down.
1: Left-channel DAC is powered up. |
D6 | R/W | 0 | 0: Right-channel DAC is powered down.
1: Right-channel DAC is powered up. |
D5–D4 | R/W | 01 | 00: Left-channel DAC data path = off
01: Left-channel DAC data path = left data 10: Left-channel DAC data path = right data 11: Left-channel DAC data path = left-channel and right-channel data [(L + R) / 2] |
D3–D2 | R/W | 01 | 00: Right-channel DAC data path = off
01: Right-channel DAC data path = right data 10: Right-channel DAC data path = left data 11: Right-channel DAC data path = left-channel and right-channel data [(L + R) / 2] |
D1–D0 | R/W | 00 | 00: DAC-channel volume-control soft-stepping is enabled for one step per sample period.
01: DAC-channel volume-control soft-stepping is enabled for one step per two sample periods. 10: DAC-channel volume-control soft-stepping is disabled. 11: Reserved. Do not write this sequence to these bits. |
BIT | READ/
WRITE |
RESET
VALUE |
DESCRIPTION |
---|---|---|---|
D7–D4 | R/W | 0000 | Reserved. Write only zeros to these bits. |
D3 | R/W | 1 | 0: Left-channel DAC not muted
1: Left-channel DAC muted |
D2 | R/W | 1 | 0: Right-channel DAC not muted
1: Right-channel DAC muted |
D1–D0 | R/W | 00 | 00: Left and right channels have independent volume control.(1)
01: Left-channel volume control Is the programmed value of right-channel volume control. 10: Right-channel volume control is the programmed value of left-channel volume control. 11: Same as 00 |
BIT | READ/
WRITE |
RESET
VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | 0000 0000 | Left DAC Channel Digital Volume Control Setting
0111 1111–0011 0001: Reserved. Do not use 0011 0000: Digital volume control = 24 dB 0010 1111: Digital volume control = 23.5 dB 0010 1110: Digital volume control = 23 dB ... 0000 0001: Digital volume control = 0.5 dB 0000 0000: Digital volume control = 0 dB 1111 1111: Digital volume control = –0.5 dB ... 1000 0010: Digital volume control = –63 dB 1000 0001: Digital volume control = –63.5 dB 1000 0000: Reserved. |
BIT | READ/
WRITE |
RESET
VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | 0000 0000 | Right DAC Channel Digital Volume Control Setting
0111 1111–0011 0001: Reserved. Do not use 0011 0000: Digital volume control = 24 dB 0010 1111: Digital volume control = 23.5 dB 0010 1110: Digital volume control = 23 dB ... 0000 0001: Digital volume control = 0.5 dB 0000 0000: Digital volume control = 0 dB 1111 1111: Digital volume control = –0.5 dB ... 1000 0010: = –63 dB 1000 0001: = –63.5 dB 1000 0000: Reserved. |
BIT | READ/
WRITE |
RESET
VALUE |
DESCRIPTION |
---|---|---|---|
D7 | R/W | 0 | 0: Headset detection disabled
1: Headset detection enabled |
D6–D5 | R | XX | 00: No headset detected
01: Headset without microphone is detected 10: Reserved 11: Headset with microphone is detected |
D4–D2 | R/W | 000 | Debounce Programming for Glitch Rejection During Headset Detection(1)
000: 16 ms (sampled with 2-ms clock) 001: 32 ms (sampled with 4-ms clock) 010: 64 ms (sampled with 8-ms clock) 011: 128 ms (sampled with 16-ms clock) 100: 256 ms (sampled with 32-ms clock) 101: 512 ms (sampled with 64-ms clock) 110: Reserved 111: Reserved |
D1–D0 | R/W | 00 | Debounce programming for glitch rejection during headset button-press detection
00: 0 ms 01: 8 ms (sampled with 1-ms clock) 10: 16 ms (sampled with 2-ms clock) 11: 32 ms (sampled with 4-ms clock) |
BIT | READ/
WRITE |
RESET
VALUE |
DESCRIPTION |
---|---|---|---|
D7 | R/W | 0 | Reserved. Write only the reset value to these bits. |
D6 | R/W | 0 | 0: DRC disabled for left channel
1: DRC enabled for left channel |
D5 | R/W | 0 | 0: DRC disabled for right channel
1: DRC enabled for right channel |
D4–D2 | R/W | 011 | 000: DRC threshold = –3 dB
001: DRC threshold = –6 dB 010: DRC threshold = –9 dB 011: DRC threshold = –12 dB 100: DRC threshold = –15 dB 101: DRC threshold = –18 dB 110: DRC threshold = –21 dB 111: DRC threshold = –24 dB |
D1–D0 | R/W | 11 | 00: DRC hysteresis = 0 dB
01: DRC hysteresis = 1 dB 10: DRC hysteresis = 2 dB 11: DRC hysteresis = 3 dB |
BIT | READ/
WRITE |
RESET
VALUE |
DESCRIPTION |
---|---|---|---|
D7 | R/W | 0 | 0: Beep generator is disabled.
1: Beep generator is enabled (self-clearing based on beep duration). |
D6 | R/W | 0 | Reserved. Write only reset value. |
D5–D0 | R/W | 00 0000 | 00 0000: Left-channel beep volume control = 2 dB
00 0001: Left-channel beep volume control = 1 dB 00 0010: Left-channel beep volume control = 0 dB 00 0011: Left-channel beep volume control = –1 dB ... 11 1110: Left-channel beep volume control = –60 dB 11 1111: Left-channel beep volume control = –61 dB |
BIT | READ/
WRITE |
RESET
VALUE |
DESCRIPTION |
---|---|---|---|
D7–D6 | R/W | 00 | 00: Left and right channels have independent beep volume control.
01: Left-channel beep volume control is the programmed value of right-channel beep volume control. 10: Right-channel beep volume control is the programmed value of left-channel beep volume control. 11: Same as 00 |
D5–D0 | R/W | 00 0000 | 00 0000: Right-channel beep volume control = 2 dB
00 0001: Right-channel beep volume control = 1 dB 00 0010: Right-channel beep volume control = 0 dB 00 0011: Right-channel beep volume control = –1 dB ... 11 1110: Right-channel beep volume control = –60 dB 11 1111: Right-channel beep volume control = –61 dB |
BIT | READ/
WRITE |
RESET
VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | 0000 0000 | 8 MSBs out of 24 bits for the number of samples for which the beep must be generated. |
BIT | READ/
WRITE |
RESET
VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | 0000 0000 | 8 middle bits out of 24 bits for the number of samples for which the beep must be generated. |
BIT | READ/
WRITE |
RESET
VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | 1110 1110 | 8 LSBs out of 24 bits for the number of samples for which beep must be generated. |
BIT | READ/
WRITE |
RESET
VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | 0001 0000 | 8 MSBs out of 16 bits for sin(2π × fin / fS), where fin is the beep frequency and fS is the DAC sample rate. |
BIT | READ/
WRITE |
RESET
VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | 1101 1000 | 8 LSBs out of 16 bits for sin(2π × fin / fS), where fin is the beep frequency and fS is the DAC sample rate. |
BIT | READ/
WRITE |
RESET
VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | 0111 1110 | 8 MSBs out of 16 bits for cos(2π × fin / fS), where fin is the beep frequency and fS is the DAC sample rate. |
BIT | READ/
WRITE |
RESET
VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | 1110 0011 | 8 LSBs out of 16 bits for cos(2π × fin / fS), where fin is the beep frequency and fS is the DAC sample rate. |
BIT | READ/
WRITE |
RESET
VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | XXXX XXXX | Reserved. Do not write to these registers. |
BIT | READ/
WRITE |
RESET
VALUE |
DESCRIPTION | ||
---|---|---|---|---|---|
D7 | R/W | 0 | 0: DAC volume control is controlled by control register. (7-bit Vol ADC is powered down)
1: DAC volume control is controlled by pin. |
||
D6 | R/W | 0 | 0: Internal on-chip RC oscillator is used for the 7-bit Vol ADC for pin volume control.
1: MCLK is used for the 7-bit Vol ADC for pin volume control. |
||
D5–D4 | R/W | 00 | 00: No hysteresis for volume control ADC output
01: Hysteresis of ±1 bit 10: Hysteresis of ±2 bits 11: Reserved. Do not write this sequence to these bits. |
||
D3 | R/W | 0 | Reserved. Write only reset value. | ||
D2–D0 | R/W | 000 | Throughput of the 7-bit Vol ADC for pin volume control, frequency based on MCLK or internal oscillator. | ||
MCLK = 12 MHz | Internal Oscillator Source | ||||
000: Throughput =
001: Throughput = 010: Throughput = 011: Throughput = 100: Throughput = 101: Throughput = 110: Throughput = 111: Throughput = |
15.625 Hz
31.25 Hz 62.5 Hz 125 Hz 250 Hz 500 Hz 1 kHz 2 kHz |
10.68 Hz
21.35 Hz 42.71 Hz 8.2 Hz 170 Hz 340 Hz 680 Hz 1.37 kHz Note: These values are based on a nominal oscillator frequency of 8.2 MHz. The values scale to the actual oscillator frequency. |
BIT | READ/
WRITE |
RESET
VALUE |
DESCRIPTION |
---|---|---|---|
D7 | R/W | 0 | Reserved. Write only zero to this bit. |
D6–D0 | R | XXX XXXX | 000 0000: Gain applied by pin volume control = 18 dB
000 0001: Gain applied by pin volume control = 17.5 dB 000 0010: Gain applied by pin volume control = 17 dB ... 010 0011: Gain applied by pin volume control = 0.5 dB 010 0100: Gain applied by pin volume control = 0 dB 010 0101: Gain applied by pin volume control = –0.5 dB ... 101 1001: Gain applied by pin volume control = –26.5 dB 101 1010: Gain applied by pin volume control = –27 dB 101 1011: Gain applied by pin volume control = –28 dB ... 111 1101: Gain applied by pin volume control = –62 dB 111 1110: Gain applied by pin volume control = –63 dB 111 1111: Reserved. |
BIT | READ/
WRITE |
RESET
VALUE |
DESCRIPTION |
---|---|---|---|
D7–D0 | R/W | XXXX XXXX | Reserved. Do not write to these registers. |