SLVS568D January   2005  – April 2016 TLV341 , TLV341A , TLV342 , TLV342S

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information: TLV341
    5. 6.5  Thermal Information: TLV342
    6. 6.6  Thermal Information: TLV342S
    7. 6.7  Electrical Characteristics: V+ = 1.8 V
    8. 6.8  Electrical Characteristics: V+ = 5 V
    9. 6.9  Shutdown Characteristics: V+ = 1.8 V
    10. 6.10 Shutdown Characteristics: V+ = 5 V
    11. 6.11 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 PMOS Input Stage
      2. 7.3.2 CMOS Output Stage
      3. 7.3.3 Shutdown
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Related Links
    2. 11.2 Community Resource
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Detailed Description

7.1 Overview

The TLV34xx devices are precision operational amplifiers with CMOS inputs for very low input bias current. Grade A devices offer lower VIO for high accuracy in direct-coupled applications. Output is rail to rail and input common mode includes ground. TLV341 and TLV342S have shutdown mode for very low supply current.

7.2 Functional Block Diagram

TLV341 TLV341A TLV342 TLV342S BLOCK2.gif

7.3 Feature Description

7.3.1 PMOS Input Stage

PMOS Input Stage supports a lower input range that includes ground. Upper range limit is VCC – 0.6 V.

7.3.2 CMOS Output Stage

The CMOS drain output topology allows rail-to-rail output swing.

7.3.3 Shutdown

TLV341 and TLV342S include a shutdown pin. During shutdown, ICC is nearly zero and the output becomes high impedance. The typical turnon time coming out of shutdown is 5 µs.

7.4 Device Functional Modes

The TLV34xx devices have two operation modes:

  • Normal operation when SHDN pin is at V+ level or the SHDN pin is not present
  • Shutdown mode when SHDN is at GND level; ICC is very low and output is high impedance.