SNOSDD7C December   2021  – December 2023 TLV3801 , TLV3802 , TLV3811

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Thermal Information
    4. 6.4 Recommended Operating Conditions
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Diagrams
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 Inputs
      2. 7.4.2 LVDS Output
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Capacitive Loads
      2. 8.1.2 Hysteresis
    2. 8.2 Typical Application
      1. 8.2.1 Optical Receiver
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Performance Plots
      2. 8.2.2 Non-Inverting Comparator With Hysteresis
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Performance Plots
      3. 8.2.3 Logic Clock Source to LVDS Transceiver
      4. 8.2.4 External Trigger Function for Oscilloscopes
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.4.1 Inputs

The TLV380x/TLV3811(C) feature an input stage, capable of operating between 1.5 V above VEE (GND for TLV3811(C)) and 0.1 V above VCC, with an internal ESD protection circuit that includes two pairs of front-to-back diodes between IN+ and IN- as well as two 50 Ω resistors, as shown in Figure 7-1. This prevents damage to the input stage by limiting the differential input voltage to be no more than twice the diode's forward-voltage drop 2 × VF (2 × 0.7 V).

GUID-20211008-SS0I-KGD6-60JH-6SG5XRT3XXTZ-low.svgFigure 7-1 Input Stage Circuitry.
When the differential input voltage exceeds 2 × VF, the input bias current increases at the input pins IN+ and IN-, as shown in Equation 5.

Equation 1. Input Current = [(VIN+ - VIN-) - 2 × VF] / (2 × 50)
To avoid damaging the inputs when exceeding the recommended input voltage range, an external resistor should be used to limit the current. The current should be limited to less than 10 mA.