SBOSA91B December   2021  – December 2023 TLV2387 , TLV387 , TLV4387

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information: TLV387
    5. 5.5 Thermal Information: TLV2387
    6. 5.6 Thermal Information: TLV4387
    7. 5.7 Electrical Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Input Bias Current
      2. 6.3.2 EMI Susceptibility and Input Filtering
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Zero-Drift Clocking
    2. 7.2 Typical Applications
      1. 7.2.1 Bidirectional Current Sensing
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curve
      2. 7.2.2 Load Cell Measurement
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 PSpice® for TI
        2. 8.1.1.2 TINA-TI™ Simulation Software (Free Download)
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DBV|5
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.1.1 Zero-Drift Clocking

The TLVx387 use an advanced zero-drift architecture to achieve ultra-low offset and offset drift. This architecture uses a clock and switches internally to create a dc error-correction path. The clocking is filtered internally, and typically not observable for most configurations. Take the following precautions to minimize clock noise in the signal chain. The clocking creates a small charge-injection pulse at the input of the amplifier; therefore, do not use high-value resistors (> 100 kΩ) in series with the inputs to avoid higher clock voltage noise at the output. The charge injection pulses are minimized when the impedance to the input pins is matched. If higher value resistors are used, then use matching impedances on both amplifier input pins.