SBOSA91B December   2021  – December 2023 TLV2387 , TLV387 , TLV4387

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information: TLV387
    5. 5.5 Thermal Information: TLV2387
    6. 5.6 Thermal Information: TLV4387
    7. 5.7 Electrical Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Input Bias Current
      2. 6.3.2 EMI Susceptibility and Input Filtering
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Zero-Drift Clocking
    2. 7.2 Typical Applications
      1. 7.2.1 Bidirectional Current Sensing
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curve
      2. 7.2.2 Load Cell Measurement
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 PSpice® for TI
        2. 8.1.1.2 TINA-TI™ Simulation Software (Free Download)
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DBV|5
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.7 Electrical Characteristics

at TA = 25°C, RL = 10 kΩ connected to VS / 2, VS = 1.7 V to 5.5 V, VCM = VS / 2, VOUT = VS / 2, and min and max specification established from manufacturing final test (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
VOS Input offset voltage VS = 5.5 V ±1 ±5 µV
VS = 1.7 V ±1.25 ±6
dVOS/dT Input offset voltage drift TA = –40°C to +125°C(1) ±0.01 ±0.05 μV/°C
PSRR Power supply rejection ratio ±0.05 ±0.5 μV/V
TA = –40°C to +125°C(1) ±1
INPUT BIAS CURRENT
IB Input bias current ±60 ±300 pA
TA = –40°C to +125°C(1) ±350
IOS Input offset current ±60 ±500 pA
TA = –40°C to +125°C(1) ±700
NOISE
  Input voltage noise f = 0.1 Hz to 10 Hz   177   nVPP
  27   nVRMS
eN Input voltage noise density f = 1 Hz   8.5   nV/√Hz
f = 10 Hz   8.5  
f = 100 Hz   8.5  
f = 1 kHz   8.5  
iN Input current noise f = 1 kHz   70   fA/√Hz
INPUT VOLTAGE
VCM Common-mode voltage range VS = 1.7 V (V–) – 0.1 (V+) V
VS = 5.5 V (V–) – 0.2 (V+) + 0.1
CMRR Common-mode rejection ratio (V–) – 0.1 V < VCM < (V+), VS = 1.7 V 115 138 dB
(V–) – 0.2 V < VCM < (V+) + 0.1 V, VS = 5.5 V 130 150
(V–) – 0.1 V < VCM < (V+), TA = –40°C to +125°C(1) 110 132
(V–) – 0.2 V < VCM < (V+) + 0.1, VS = 5.5 V, 
TA = –40°C to +125°C(1)		 130
INPUT CAPACITANCE
ZID Differential 100 || 3 MΩ || pF
ZICM Common-mode 60 || 3 GΩ || pF
OPEN-LOOP GAIN
AOL Open-loop voltage gain (V–) + 100 mV < VOUT <
(V+) – 100 mV		 120 145 dB
TA = –40°C to +125°C(1) 115
(V–) + 150 mV < VOUT <
(V+) – 150 mV,
RL = 2 kΩ		 120 145
TA = –40°C to +125°C(1) 115
FREQUENCY RESPONSE
GBW Gain-bandwidth product 5.7 MHz
SR Slew rate 4-V step, G = +1 2.8 V/μs
tS Settling time To 0.1%, 1-V step, G = +1 1.5 μs
To 0.01%, 1-V step, G = +1 2.5
Overload recovery time VIN × G > VS 500 ns
Chopping clock frequency(1) 100 150 kHz
THD+N Total harmonic distortion + noise VOUT = 1 VRMS, G = +1, f = 1 kHz, RL = 10 kΩ 0.002 %
OUTPUT
Voltage output swing from rail no load 1 20 mV
5 30
RL = 2 kΩ 20 75
TA = –40°C to +125°C(1) 30
High linearity output swing range(1) AOL > 120 dB (V–) + 0.075 (V+) – 0.075 V
RL = 2 kΩ (V–) + 0.150 (V+) – 0.150
ISC Short-circuit current VS = 5.5 V ±55 mA
VS = 1.7 V ±15
Phase margin CL = 100 pF, G = +1 40 degrees
POWER SUPPLY
IQ Quiescent current per amplifier IO = 0 mA 570 675 μA
TA = –40°C to 125°C(1) 700 μA
Turn-on time VS = 5.5 V,
VS ramp rate > 0.3 V/µs, settle to 1%		 25 100 μs
(1) Specification established from device population bench system measurements across multiple lots.