SNVSBU0 October   2020 TLV4062-Q1 , TLV4082-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 Inputs (IN1, IN2)
      2. 7.4.2 Outputs (OUT1, OUT2)
      3. 7.4.3 Switching Threshold and Hysteresis
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Threshold Overdrive
    2. 8.2 Typical Applications
      1. 8.2.1 Monitoring Two Separate Rails
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Early Warning Detection
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curve
      3. 8.2.3 Additional Application Information
        1. 8.2.3.1 Pull-Up Resistor Selection
        2. 8.2.3.2 INx Capacitor
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.4.2 Outputs (OUT1, OUT2)

The TLV4062-Q1 features push-pull output stages which eliminates the need for an external pull-up resistor, thus saving board space, while providing a low impedance output driver. The logic high level of the outputs is determined by the V+ pin voltage.

The TLV4082-Q1 features open-drain output stages which enables the output logic levels to be pulled-up to an external source as high as 5.5 V independent of the supply voltage. Pull-up resistors must be used to hold these lines high when the output goes to a high-impedance condition (not asserted). By connecting pull-up resistors to the proper voltage rails, the outputs can be connected to other devices at correct interface voltage levels. To ensure proper voltage levels, make sure to choose the correct pull-up resistor values. The pull-up resistor value is determined by VOL, the sink current capability, and the output leakage current (Ilkg(OD)). These values are specified in the Section 6.5 table. By using wired-OR logic, OUT1 and OUT2 can be combined into one logic signal. The Section 7.4.1 section describes how the outputs are asserted or de-asserted. See Figure 6-1 for a description of the relationship between threshold voltages and the respective output.