SBOS934A August   2018  – December 2018 TLV6001-Q1 , TLV6002-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     CMRR and PSRR vs Temperature
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions: TLV6001-Q1
    2.     Pin Functions: TLV6002-Q1
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information: TLV6001-Q1
    5. 6.5 Thermal Information: TLV6002-Q1
    6. 6.6 Electrical Characteristics: VS = 1.8 V to 5 V (±0.9 V to ±2.75 V)
    7. 6.7 Typical Characteristics: Table of Graphs
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Operating Voltage
      2. 7.3.2 Rail-to-Rail Input
      3. 7.3.3 Rail-to-Rail Output
      4. 7.3.4 Common-Mode Rejection Ratio (CMRR)
      5. 7.3.5 Capacitive Load and Stability
      6. 7.3.6 EMI Susceptibility and Input Filtering
    4. 7.4 Device Functional Modes
    5. 7.5 Input and ESD Protection
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 System Examples
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example: Single Channel
    3. 10.3 Layout Example: Dual Channel
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Related Links
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|8
  • DGK|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.6 Electrical Characteristics: VS = 1.8 V to 5 V (±0.9 V to ±2.75 V)(1)


at TA = 25°C, RL = 10 kΩ connected to VS / 2, and VCM = VOUT = VS / 2 (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
VOS Input offset voltage 0.75 4.5 mV
dVOS/dT VOS vs temperature TA = –40°C to +125°C 2 µV/°C
PSRR Power-supply rejection ratio 86 dB
INPUT BIAS CURRENT
IB Input bias current TA = 25°C ±1 pA
IOS Input offset current ±1 pA
INPUT IMPEDANCE
ZID Differential 100 || 1 MΩ || pF
ZIC Common-mode 1 || 5 1013Ω || pF
INPUT VOLTAGE RANGE
VCM Common-mode voltage range No phase reversal, rail-to-rail input (V–) – 0.2 (V+) + 0.2 V
CMRR Common-mode rejection ratio VCM = –0.2 V to 5.7 V 60 76 dB
OPEN-LOOP GAIN
AOL Open-loop voltage gain 0.3 V < VO < (V+) – 0.3 V, RL = 2 kΩ 90 110
Phase margin VS = 5 V, G = 1 65 °
OUTPUT
VO Voltage output swing from supply rails RL = 100 kΩ 5 mV
RL = 2 kΩ 75 100
ISC Short-circuit current ±15 mA
RO Open-loop output impedance 2300 Ω
FREQUENCY RESPONSE
GBW Gain-bandwidth product 1 MHz
SR Slew rate 0.5 V/µs
tS Settling time To 0.1%, VS = 5 V, 2-V step , G = +1 5 µs
NOISE
Input voltage noise (peak-to-peak) f = 0.1 Hz to 10 Hz 6 µVPP
en Input voltage noise density f = 1 kHz 28 nV/√Hz
in Input current noise density f = 1 kHz 5 fA/√Hz
POWER SUPPLY
VS Specified voltage range 1.8 (±0.9) 5.5 (±2.75) V
IQ Quiescent current per amplifier IO = 0 mA, VS = 5 V 75 100 µA
Power-on time VS = 0 V to 5 V, to 90% IQ level 10 µs
(1) Parameters with minimum or maximum specification limits are 100% production tested at 25°C, unless otherwise noted. Overtemperature limits are based on characterization and statistical analysis.