SLVSIA2 November   2024 TLV61220A

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
    1.     Pin Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Controller Circuit
        1. 8.3.1.1 Startup
        2. 8.3.1.2 Operation at Output Overload
        3. 8.3.1.3 Undervoltage Lockout
        4. 8.3.1.4 Overvoltage Protection
        5. 8.3.1.5 Overtemperature Protection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Enable and Shutdown Mode
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Adjustable Output Voltage Version
        2. 9.2.2.2 Inductor Selection
        3. 9.2.2.3 Capacitor Selection
          1. 9.2.2.3.1 Input Capacitor
          2. 9.2.2.3.2 Output Capacitor
      3. 9.2.3 Application Curves
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  13. 12Device and Documentation Support
    1. 12.1 Third-Party Products Disclaimer
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  14. 13Revision History
  15.   Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.1 Overview

The TLV61220A is a high performance, highly efficient boost converter. To achieve high efficiency the power stage is realized as a synchronous boost topology. For the power switching two actively controlled low RDS(on) power MOSFETs are implemented.