SBVS161A november   2011  – april 2023 TLV701

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Wide Supply Range
      2. 7.3.2 Low Quiescent Current
      3. 7.3.3 Dropout Voltage (VDO)
      4. 7.3.4 Current Limit
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Dropout Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 External Capacitor Requirements
        2. 8.2.2.2 Input and Output Capacitor Requirements
        3. 8.2.2.3 Reverse Current
        4. 8.2.2.4 Power Dissipation (PD)
        5. 8.2.2.5 Estimating Junction Temperature
      3. 8.2.3 Application Curves
    3. 8.3 Best Design Practices
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
        1. 8.5.1.1 Power Dissipation
      2. 8.5.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
        1. 9.1.1.1 Evaluation Module
      2. 9.1.2 Device Nomenclature
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

over operating junction temperature range (TJ = –40°C to 125°C), VIN = VOUT(nom) + 1 V, IOUT = 1 mA, and COUT = 1 μF (unless otherwise noted); typical values are at TJ = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN Input voltage range (1) TJ = 25°C 24 V
VOUT Output voltage range (1) TJ = 25°C 1.2 5 V
VOUT DC output accuracy(1) TJ = 25°C –2 2 %
IGND Ground pin current (legacy chip) (3)  IOUT = 0 mA, TJ = 25°C 3.2 4.5 μA
 IOUT = 100 mA, TJ = 25°C 3.2 5.5
Ground pin current (new chip)(3)  IOUT = 0 mA, TJ = 25°C 3.2 4.1
 IOUT = 100 mA, TJ = 25°C 3.4 4.5
ΔVOUT(ΔIOUT) Load regulation 1 mA < IOUT < 10 mA  6 mV
1 mA < IOUT < 50 mA  19
1 mA < IOUT < 100 mA  29 50
ΔVOUT(ΔVIN) Line regulation (1) VOUT(NOM) + 1 V ≤ VIN ≤ 24 V , TJ = 25°C 20 50 mV
ICL Output current limit (legacy chip)  VOUT = 0 V , TJ = 25°C 160 1000 mA
Output current limit (new chip)  160 500
PSRR Power-supply ripple rejection f = 100 kHz, COUT = 10 μF 60 dB
VDO Dropout voltage VIN = VOUT(nom) – 0.1 V, IOUT = 10 mA 75 mV
VIN = VOUT(nom) – 0.1 V, IOUT = 50 mA 400
(1) Minimum VIN = VOUT + VDO or the value shown for Input voltage in this table, whichever is greater.
(2) This device employs a leakage null control circuit. This circuit is active only if output current is less than pass transistor leakage current. The circuit is typically active when output load is less than 5 μA, VIN is greater than 18 V, and die temperature is greater than 100°C.