The TLV703 series of low-dropout (LDO) linear regulators are low quiescent current devices with excellent line and load transient performance. These LDOs are designed for power-sensitive applications. A precision band-gap and error amplifier provides overall 2% accuracy. Low output noise, very high power-supply rejection ratio (PSRR), and low-dropout voltage make this series of devices ideal for a wide selection of battery-operated handheld equipment. All device versions have thermal shutdown and current limit for safety.
Furthermore, these devices are stable with an effective output capacitance of only 0.1 µF. This feature enables the use of cost-effective capacitors that have higher bias voltages and temperature derating. The devices regulate to specified accuracy with no output load.
The TLV703 series of LDO linear regulators are available in a 5-pin SOT-23 package.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TLV703 | SOT-23 (5) | 2.90 mm × 1.60 mm |
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DATE | REVISION | NOTES |
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March 2017 | * | Initial release. |
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NO. | NAME | ||
1 | IN | I | Input pin. A small, 1-µF ceramic capacitor is recommended from this pin to ground to assure stability and good transient performance. See the in the Application Information section for more details. |
2 | GND | — | Ground pin |
3 | EN | I | Enable pin. Driving EN over 0.9 V turns on the regulator. Driving EN below 0.4 V puts the regulator into shutdown mode and reduces operating current to 1 µA, nominal. |
4 | NC | — | No connection. This pin can be tied to ground to improve thermal dissipation. |
5 | OUT | O | Regulated output voltage pin. A small, 1-µF ceramic capacitor is needed from this pin to ground to assure stability. See the in the Application Information section for more details. |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Voltage(2) | IN, EN, OUT | –0.3 | 6 | V |
Current (source) | OUT | Internally limited | ||
Output short-circuit duration | Indefinite | |||
Total continuous power dissipation | See Thermal Information | |||
Temperature | Operating virtual junction, TJ | –55 | 150 | °C |
Storage, Tstg | –55 | 150 |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
Charged device model (CDM), per JEDEC specification JESD22-C101(2) | ±500 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
VIN | Input voltage range | 2 | 5.5 | V | |
VOUT | Output voltage range | 1.2 | 4.8 | V | |
IOUT | Output current | 0 | 300 | mA |
THERMAL METRIC(1) | TLV703 | UNIT | |
---|---|---|---|
DBV (SOT-23) | |||
5 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 254.1 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 143.9 | °C/W |
RθJB | Junction-to-board thermal resistance | 58.0 | °C/W |
ψJT | Junction-to-top characterization parameter | 25.3 | °C/W |
ψJB | Junction-to-board characterization parameter | 56.6 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | N/A | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |||
---|---|---|---|---|---|---|---|---|
VIN | Input voltage range | 2 | 5.5 | V | ||||
VOUT | DC output accuracy | –40°C ≤ TJ ≤ 125°C | –2% | 0.5% | 2% | |||
ΔVOUT(ΔVIN) | Line regulation | VOUT(nom) + 0.5 V ≤ VIN ≤ 5.5 V, IOUT = 10 mA |
1 | 5 | mV | |||
ΔVOUT(ΔIOUT) | Load regulation | 0 mA ≤ IOUT ≤ 300 mA | 1 | 15 | mV | |||
VDO | Dropout voltage(1) | VIN = 0.98 × VOUT(nom), IOUT = 300 mA | 260 | 375 | mV | |||
ICL | Output current limit | VOUT = 0.9 × VOUT(nom) | 320 | 500 | 860 | mA | ||
IGND | Ground pin current | IOUT = 0 mA | 35 | 55 | µA | |||
IOUT = 300 mA, VIN = VOUT + 0.5 V | 370 | |||||||
ISHDN | Ground pin current (shutdown) | VEN ≤ 0.4 V, VIN = 2 V | 400 | nA | ||||
VEN ≤ 0.4 V, 2 V ≤ VIN ≤ 4.5 V, TJ = –40°C to +85°C |
1 | 2 | µA | |||||
PSRR | Power-supply rejection ratio | VIN = 2.3 V, VOUT = 1.8 V, IOUT = 10 mA, f = 1 kHz |
68 | dB | ||||
Vn | Output noise voltage | BW = 100 Hz to 100 kHz, VIN = 2.3 V, VOUT = 1.8 V, IOUT = 10 mA |
48 | µVRMS | ||||
tSTR | Start-up time(2) | COUT = 1 µF, IOUT = 300 mA | 100 | µs | ||||
VEN(high) | Enable pin high (enabled) | 0.9 | VIN | V | ||||
VEN(low) | Enable pin low (disabled) | 0 | 0.4 | V | ||||
IEN | Enable pin current | VIN = VEN = 5.5 V | 0.04 | µA | ||||
UVLO | Undervoltage lockout | VIN rising | 1.9 | V | ||||
Tsd | Thermal shutdown temperature | Shutdown, temperature increasing | 165 | °C | ||||
Reset, temperature decreasing | 145 | |||||||
TJ | Operating junction temperature | –40 | 125 | °C |
VOUT = 1.8 V, IOUT = 10 mA |
VOUT = 1.8 V |
VOUT = 1.8 V |
VOUT = 1.8 V |
VOUT = 1.8 V |
VIN – VOUT = 0.5 V |
VOUT = 1.8 V, IOUT = 10 mA, CIN = COUT = 1 µF |
VOUT = 1.8 V, tR = tF = 1 µs |
VOUT = 1.8 V, tR = tF = 1 µs |
VOUT = 1.8 V, IOUT = 1 mA, slew rate = 1 V/µs |
VOUT = 1.8 V, IOUT = 1 mA |
VOUT = 1.8 V, IOUT = 300 mA |
IOUT = 300 mA |
VOUT = 1.8 V |
VOUT = 1.8 V |
VOUT = 1.8 V |
VOUT = 1.8 V |
VOUT = 1.8 V | ||
VOUT = 1.8 V, tR = tF = 1 µs |
VOUT = 1.8 V, IOUT = 300 mA, slew rate = 1 V/µs |
VOUT = 1.8 V, IOUT = 300 mA, slew rate = 1 V/µs |
The TLV703 series of low-dropout (LDO) linear regulators are low quiescent current devices with excellent line and load transient performance. These LDOs are designed for power-sensitive applications. A precision band-gap and error amplifier provides overall 2% accuracy. Low output noise, very high power-supply rejection ratio (PSRR), and low dropout voltage make this series of devices ideal for most battery-operated handheld equipment. All device versions have integrated thermal shutdown, current limit, and undervoltage lockout (UVLO).
The TLV703 internal current limit helps protect the regulator during fault conditions. During current limit, the output sources a fixed amount of current that is largely independent of the output voltage. In such a case, the output voltage is not regulated, and is VOUT = ICL × RLOAD. The PMOS pass transistor dissipates (VIN – VOUT) × ICL until thermal shutdown is triggered and the device turns off. As the device cools, the internal thermal shutdown circuit turns the device back on. If the fault condition continues, the device cycles between current limit and thermal shutdown; see the Thermal Consideration section for more details.
The PMOS pass element in the TLV703 has a built-in body diode that conducts current when the voltage at OUT exceeds the voltage at IN. This current is not limited, so if extended reverse voltage operation is anticipated, external limiting to 5% of the rated output current is recommended.
The enable pin (EN) is active high. The device is enabled when voltage at the EN pin goes above 0.9 V. The device is turned off when the EN pin is held at less than 0.4 V. When shutdown capability is not required, EN can be connected to the IN pin.
The TLV703 uses a PMOS pass transistor to achieve low dropout. When (VIN – VOUT) is less than the dropout voltage (VDO), the PMOS pass device is in the linear (triode) region of operation and the input-to-output resistance is the RDS(on) of the PMOS pass element. VDO scales approximately with output current because the PMOS device functions as a resistor in dropout.
As with any linear regulator, PSRR and transient response are degraded when (VIN – VOUT) approaches dropout. Figure 12 illustrates this effect.
The TLV703 uses a UVLO circuit to keep the output shut off until internal circuitry is operating properly.
The device regulates to the nominal output voltage under the following conditions:
If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other conditions are met for normal operation, the device operates in dropout mode. In this condition, the output voltage is the same as the input voltage minus the dropout voltage. The transient performance of the device is significantly degraded because the pass device is in a triode state and no longer regulates the output voltage of the LDO. Line or load transients in dropout can result in large output voltage deviations.
Table 1 lists the conditions that lead to the different modes of operation.
OPERATING MODE | PARAMETER | |
---|---|---|
VIN | IOUT | |
Normal mode | VIN > VOUT (nom) + VDO | IOUT < ICL |
Dropout mode | VIN < VOUT (nom) + VDO | IOUT < ICL |
Current limit | VIN > UVLO | IOUT > ICL |
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The TLV703 belongs to a family of next-generation value LDO regulators. These devices consume low quiescent current and deliver excellent line and load transient performance. These characteristics, combined with low noise and very good PSRR with little (VIN – VOUT) headroom, make this family of devices ideal for portable RF applications. This family of regulators offers current limit and thermal protection, and is specified from –40°C to +125°C.
Table 2 lists the design parameters.
PARAMETER | DESIGN REQUIREMENT |
---|---|
Input voltage | 2.5 V to 3.3 V |
Output voltage | 1.8 V |
Output current | 100 mA |
1-μF X5R- and X7R-type ceramic capacitors are recommended because these capacitors have minimal variation in value and equivalent series resistance (ESR) over temperature.
However, the TLV703 is designed to be stable with an effective capacitance of 0.1 μF or larger at the output. Thus, the device is stable with capacitors of other dielectric types as well, as long as the effective capacitance under operating bias voltage and temperature is greater than 0.1 µF. In addition to allowing the use of lower-cost dielectrics, this capability of being stable with 0.1-µF effective capacitance also enables the use of smaller footprint capacitors that have higher derating in size- and space-constrained applications.
Using a 0.1-µF rated capacitor at the output of the LDO does not ensure stability because the effective capacitance under the specified operating conditions must not be less than 0.1 µF. Maximum ESR must be less than 200 mΩ.
Although an input capacitor is not required for stability, good analog design practice is to connect a 0.1-µF to
1-µF, low ESR capacitor across the IN pin and GND pin of the regulator. This capacitor counteracts reactive input sources and improves transient response, noise rejection, and ripple rejection. A higher-value capacitor may be necessary if large, fast rise-time load transients are anticipated, or if the device is not located close to the power source. If source impedance is more than 2 Ω, a 0.1-μF input capacitor may be necessary to ensure stability.
As with any regulator, increasing the size of the output capacitor reduces overshoot and undershoot magnitude but increases the duration of the transient response.
VOUT = 1.8 V, tR = tF = 1 µs |
VOUT = 1.8 V, IOUT = 1 mA, slew rate = 1 V/µs |
Connect a low output impedance power supply directly to the IN pin of the TLV703. Inductive impedances between the input supply and the IN pin can create significant voltage excursions at the IN pin during start-up or load transient events.
The ability to remove heat from the die is different for each package type, presenting different considerations in the printed-circuit-board (PCB) layout. The PCB area around the device that is free of other components moves the heat from the device to the ambient air; see the Thermal Information section for thermal performance on the TLV703 evaluation module (EVM). The EVM is a two-layer board with two ounces of copper per side.
Power dissipation depends on input voltage and load conditions. Equation 1 shows that power dissipation (PD) is equal to the product of the output current and the voltage drop across the output pass element.