10.1 Layout Guidelines

Place input and output capacitors as close to the device pins as possible. To improve ac performance (such as PSRR, output noise, and transient response), TI recommends designing the board with the input and output capacitors on opposite sides of the device. In addition, connect the ground connection for the output capacitor directly to the GND pin of the device. High ESR capacitors can degrade PSRR.

10.2 Layout Example

Figure 31. Example PCB Layout

10.3 Power Dissipation

The ability to remove heat from the die is different for each package type, presenting different considerations in the printed-circuit-board (PCB) layout. The PCB area around the device that is free of other components moves the heat from the device to the ambient air. Performance data for JEDEC low and high-K boards are given in Thermal Information. Using heavier copper increases the effectiveness in removing heat from the device. The addition of plated through-holes to heat-dissipating layers also improves the thermal dissipation.

See for thermal performance on the TLV705 evaluation module (EVM). The EVM is a 2-layer board with two ounces of copper per side.

Power dissipation depends on input voltage and load conditions. Power dissipation (P_D) is equal to the product of the output current and the voltage drop across the output pass element, as shown in Equation 3:

10.4 Power Dissipation and Junction Temperature

Thermal protection disables the output when the junction temperature rises to approximately 160°C, allowing the device to cool. When the junction temperature cools to approximately 140°C, the output circuitry is enabled again. Depending on power dissipation, thermal resistance, and ambient temperature, the thermal protection circuit can cycle on and off. This cycling limits the dissipation of the regulator, which protects the regulator from damage as a result of overheating.

For reliable operation, limit junction temperature to 125°C (maximum). To estimate the margin of safety in a complete design, increase the ambient temperature until the thermal protection is triggered; use worst-case loads and signal conditions. For good reliability, trigger thermal protection at least 35°C above the maximum expected ambient condition of the particular application. This configuration produces a worst-case junction temperature of 125°C at the highest expected ambient temperature and worst-case load.

The internal protection circuitry of the TLV705 is designed to protect against overload conditions. Continuously running the TLV705 into thermal shutdown degrades device reliability.

10.5 Estimating Junction Temperature

The JEDEC standard now recommends the use of psi (Ψ) thermal metrics to estimate the junction temperatures of the LDO when in-circuit on a typical PCB board application. These metrics are not strictly discussing thermal resistances; rather, these metrics offer practical and relative means of estimating junction temperatures. These psi metrics are determined to be significantly independent of the copper-spreading area. The key thermal metrics (Ψ_JT and Ψ_JB) are given in Thermal Information and are used in accordance with Equation 4.

Equation 4.

where

• P_D is the power dissipated, as explained in Thermal Information.
• T_T is the temperature at the center-top of the device package, and
• T_B is the PCB surface temperature measured 1 mm from the device package and centered on the package edge.