SNVSAV1A June   2017  – October 2017 TLV760

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Thermal Protection
      2. 7.3.2 Dropout Voltage
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Fixed Output
      2. 8.1.2 External Capacitors
        1. 8.1.2.1 Input and Output Capacitor Requirements
        2. 8.1.2.2 Load-Step Transient Response
      3. 8.1.3 Power Dissipation
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Related Documentation
      2. 11.1.2 Spice Models
      3. 11.1.3 Device Nomenclature
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Detailed Description

7.1 Overview

The TLV760 is an integrated linear-voltage regulator with inputs that can be as high as 30 V. The TLV760 features quasi LDO architecture, which allows the usage of low ESR capacitors at the output. A ceramic capacitor with a capacitance value greater than or equal to 0.1 µF is adequate to keep the linear regulator in stable operation. The device has a rugged active junction thermal protection mechanism.

7.2 Functional Block Diagram

TLV760 FBD-TLV760-3.gif

7.3 Feature Description

7.3.1 Thermal Protection

The TLV760 contains an active thermal protection mechanism, which limits the junction temperature to 150°C. This protection comes into action when the thermal junction temperature of the device tries to exceed 150°C. The output current of the device is limited or folded back to maintain the junction temperature.

The thermal protection follows Equation 1

Equation 1. TLV760 equation1.gif

where

  • PD = (VIN – VOUT )IOUT
  • TJ is the junction temperature
  • RθJA is the junction-to-ambient thermal resistance

When a high drop out condition occurs resulting in higher power dissipation across the device the output current is limited to maintain a constant junction temperature of 150°C. This rugged feature protects the device from higher power dissipation applications as well as the short to ground at the output.

This internal protection circuitry of TLV760 is intended to protect the devices against thermal overload conditions. The circuitry is not intended to replace proper heat sinking. Continuously running the TLV760 into thermal protection degrades device reliability.

For reliable operation, limit junction temperature to a maximum of 125°C. To estimate the thermal margin in a given layout, increase the ambient temperature until the thermal protection is triggered using worst case load and highest input voltage conditions.

7.3.2 Dropout Voltage

The TLV760 is a bipolar device with quasi LDO architecture. Being a bipolar device the dropout voltage of the device does not change significantly with output load current. The device has a maximum dropout across temperature of 1.2 V at 100-mA load current, which is a significant improvement over the traditional LM78Lxx devices.

7.4 Device Functional Modes

7.4.1 Normal Operation

The TLV760 operates with an input up to 30 V. Its tiny SOT-23 package and quasi-LDO architecture makes it suitable for providing a very tiny 100-mA bias supply. The device regulates to the nominal output voltage when all of the following conditions are met.

  • The input voltage is greater than the nominal output voltage plus the dropout voltage (VOUT(NOM) + VDO).
  • The output current is less than or equal to 100 mA.
  • The device junction temperature is less than the thermal protection temperature of 150°C.