SBVS455 April 2024 TLV772
ADVANCE INFORMATION
For this design example, the 3.3V output is set using external divider resistors. R1 = 59kΩ and R2 = 13kΩ. A nominal 4.0V input supply is assumed. Use a minimum 1μF input capacitor to minimize the effect of resistance and inductance between the 4.0V source and the LDO input. Use a minimum 0.47μF output capacitance for stability and good load transient response. The dropout voltage (VDO) is less than 255mV maximum at a 3.3V output voltage and 300mA output current. Thus, there are no dropout issues with a 3.8V minimum input voltage (4.0V − 5%) and a maximum 200mA output current.