SBVS157E April   2011  – December 2020 TLV803 , TLV853

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings (1)
    2. 7.2 ESD Ratings
    3. 7.3 Thermal Information
    4. 7.4 Recommended Operating Conditions
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 VDD Transient Rejection
      2. 8.3.2 Reset During Power Up and Power Down
      3. 8.3.3 Bidirectional Reset Pins
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation (VDD > Power-Up Reset Voltage)
      2. 8.4.2 Power On Reset (VDD < Power-Up Reset Voltage)
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Monitoring Multiple Supplies
      2. 9.1.2 Output Level Shifting
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
        1. 12.1.1.1 Evaluation Modules
        2. 12.1.1.2 Spice Models
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Related Links
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.6 Switching Characteristics

over operating temperature range (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
twPulse duration at VDDVDD = 1.08 VIT– to 0.92 VIT–10µs
tdDelay timeVDD ≥ VIT– + 0.2 V; see Timing Diagram120200280ms
GUID-66FCFD90-1109-4CB0-BFFF-C7A6221AFC1D-low.gifFigure 7-1 Timing Diagram