SNVSBY3A November   2020  – April 2021 TLV840-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Timing Diagrams
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Voltage (VDD)
        1. 8.3.1.1 VDD Hysteresis
        2. 8.3.1.2 VDD Transient Immunity
      2. 8.3.2 User-Programmable Reset Time Delay
      3. 8.3.3 Manual Reset (MR) Input
      4. 8.3.4 Output Logic
        1. 8.3.4.1 RESET Output, Active-Low
        2. 8.3.4.2 RESET Output, Active-High
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation (VDD > VPOR)
      2. 8.4.2 Below Power-On-Reset (VDD < VPOR)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design 1: Dual Rail Monitoring with Power-up Sequencing
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Application Curve: Adjusting Output Reset Delay on TLV840EVM
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Nomenclature
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.3.2 User-Programmable Reset Time Delay

The reset time delay can be set to a minimum value of 80 µs by leaving the CT pin floating, or a maximum value of approximately 6.2 seconds by connecting 10 µF delay capacitor. The reset time delay (tD) can be programmed by connecting a capacitor no larger than 10 µF between CT pin and GND.

The relationship between external capacitor (CCT) in µF at CT pin and the time delay (tD) in seconds is given by Equation 2.

Equation 2. tD (typ) = -ln (0.29) x RCT x CCT + tD (no cap)

Equation 3 solves for external capacitor (μF) by plugging RCT and tD (CT pin = Open) given in Section 7.5 section:

Equation 3. CCT = (tD - 80 µs) ÷ 618937

The reset delay varies according to three variables: the external capacitor (CCT), CT pin internal resistance (RCT) provided in Section 7.5, and a constant. The minimum and maximum variance due to the constant is show in Equation 4 and Equation 5:

Equation 4. tD (min) = -ln (0.37) x RCT (min) x CCT_EXT (min) + tD (no cap)
Equation 5. tD (max) = -ln (0.25) x RCT (max) x CCT_EXT (max) + tD (no cap)

The recommended maximum delay capacitor for the TLV840-Q1 is limited to 10 µF as this ensures there is enough time for the capacitor to fully discharge when the reset condition occurs. When a voltage fault occurs, the previously charged up capacitor discharges, and if the monitored voltage returns from the fault condition before the delay capacitor discharges completely, the reset delay will be shorter than expected because the delay capacitor will begin charging from a voltage above zero. Larger delay capacitors can be used so long as the capacitor has enough time to fully discharge during the duration of the voltage fault. The amount of time required to discharge the delay capacitor relative to the reset delay increases as VDD overdrive increases as shown in Figure 8-3. From the graph below, to ensure the CT capacitor is fully discharged, the time period or duration of the voltage fault needs to be greater than 10% of the programmed reset time delay.

GUID-239CC270-1029-49E1-9E1B-B29D670BEFBA-low.gif Figure 8-3 CCT Discharge Time During Fault Condition (VIT- = 2 V, CCT = 1 µF)