SLVSFO5E April   2020  – February 2026 TLV841

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Timing Diagrams
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Voltage (VDD)
        1. 7.3.1.1 VDD Hysteresis
        2. 7.3.1.2 VDD Transient Immunity
      2. 7.3.2 SENSE Input (TLV841S)
        1. 7.3.2.1 SENSE Hysteresis
        2. 7.3.2.2 Immunity to SENSE Pin Voltage Transients
      3. 7.3.3 User-Programmable Reset Time Delay for TLV841C Only
      4. 7.3.4 Manual Reset (MR) Input for TLV841M only
      5. 7.3.5 Output Logic
        1. 7.3.5.1 RESET Output, Active-Low
        2. 7.3.5.2 RESET Output, Active-High
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation (VDD > VPOR)
      2. 7.4.2 Below Power-On-Reset (VDD < VPOR)
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design 1: Adjustable Voltage Supervisor With Push-Button Functionality
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
      4. 8.2.4 Application Curves: TLV841EVM
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.7 Timing Diagrams

TLV841 Timing Diagram for TLV841SxxL (SENSE) Active Low Output [Open-Drain and Push-Pull Output Topology]
A. Open-Drain timing diagram assumes the RESET pin is connected via an external pull-up resistor to VDD.
Figure 6-1 Timing Diagram for TLV841SxxL (SENSE) Active Low Output
[Open-Drain and Push-Pull Output Topology]
TLV841 Timing Diagram for TLV841SxxH (SENSE) Active High Output [Open-Drain and Push-Pull Output Topology]
A. Open-Drain timing diagram assumes the RESET pin is connected via an external pull-up resistor to VDD.
Figure 6-2 Timing Diagram for TLV841SxxH (SENSE) Active High Output
[Open-Drain and Push-Pull Output Topology]
TLV841 Timing Diagram for TLV841CxxL (CT) Active Low Output [Open-Drain and Push-Pull Output Topology]
A. Open-Drain timing diagram assumes the RESET / RESET pin is connected via an external pull-up resistor to VDD.
B. tD (no cap) is included in tSTRT time delay. If tD delay is programmed by an external capacitor connected to CT pin then tD programmed time will be added to the startup time, VDD slew rate = 1V / µs.
C. Be advised that the VDD falling slew rate is (slew rate > 1V / µs) and resulting RESETin what is shown above figure. The RESET behavior would be similar to Figure 6-1 if the slew rate was much slower or if VDD decay time is larger than the prop delay (tD_HL).
Figure 6-3 Timing Diagram for TLV841CxxL (CT) Active Low Output
[Open-Drain and Push-Pull Output Topology]
TLV841 Timing Diagram for TLV841MxxL Active Low Output (MR) [Open-Drain and Push-Pull Output Topology]
A. Open-Drain timing diagram assumes the RESET / RESET pin is connected via an external pull-up resistor to VDD.
Figure 6-4 Timing Diagram for TLV841MxxL Active Low Output (MR)
[Open-Drain and Push-Pull Output Topology]