SNOSD29E December   2016  – April 2018 TLV8541 , TLV8542 , TLV8544

UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Low Power PIR Motion Detector
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
    1.     Pin Functions: TLV8541 DBV
    2.     Pin Functions: TLV8542 D & RUG
    3.     Pin Functions: TLV8544 PW & D
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
      1. 8.4.1 Rail-To-Rail Input
      2. 8.4.2 Supply Current Changes Over Common Mode
      3. 8.4.3 Design Optimization With Rail-To-Rail Input
      4. 8.4.4 Design Optimization for Nanopower Operation
      5. 8.4.5 Common-Mode Rejection
      6. 8.4.6 Output Stage
      7. 8.4.7 Driving Capacitive Load
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application: Battery-Powered Wireless PIR Motion Detectors
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Calculation of the Cutoff Frequencies and Gain of Stage A:
        2. 9.2.2.2 Calculation of the Cutoff Frequencies and Gain of Stage B
        3. 9.2.2.3 Calculation of the Total Gain of Stages A and B
        4. 9.2.2.4 Window Comparator Stage
        5. 9.2.2.5 Reference Voltages
      3. 9.2.3 Application Curve
    3. 9.3 Typical Application: 60-Hz Twin T Notch Filter
      1. 9.3.1 Design Requirements
      2. 9.3.2 Detailed Design Procedure
      3. 9.3.3 Application Curve
    4. 9.4 Dos and Don'ts
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Related Links
    4. 12.4 Receiving Notification of Documentation Updates
    5. 12.5 Community Resources
    6. 12.6 Trademarks
    7. 12.7 Electrostatic Discharge Caution
    8. 12.8 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.4 Thermal Information

THERMAL METRIC(1) TLV8544 TLV8542 TLV8541 UNIT
PW (TSSOP) D
(SOIC)		 D
(SOIC)		 RUG (X2QFN) DBV (SOT-23)
14 PINS 14 PINS 8 PINS 8 PINS 5 PINS
RθJA Junction-to-ambient thermal resistance 124.5 104.1 141.6 188.3 244.6 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 52.7 61.5 85.7 88.9 127.3 °C/W
RθJB Junction-to-board thermal resistance 66.2 59.9 84.7 100.2 79.4 °C/W
ψJT Junction-to-top characterization parameter 7.3 22.9 36.3 3.9 44.1 °C/W
ψJB Junction-to-board characterization parameter 65.7 59.5 84.0 100.3 78.8 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A N/A N/A N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.