SBOS836 Data sheet

SBOS836G March 2020 – March 2022 TLV9041 , TLV9042 , TLV9044

PRODUCTION DATA

Package Options

Mechanical Data (Package|Pins)

D|8
- MSOI002K
DSG|8
- MPDS308C
PW|8
- MPDS568
RUG|10
- MPQF216A
DGK|8
- MPDS028E
DDF|8
- MPDS569D

Thermal pad, mechanical data (Package|Pins)

DSG|8
- QFND141I
RUG|10
- QFND221

Orderable Information

7.8 Typical Characteristics

at T_A = 25°C, V+ = 2.75 V, V– = –2.75 V, R_L = 10 kΩ connected to V_S / 2, V_CM = V_S / 2, and V_OUT = V_S / 2 (unless otherwise noted)

V_S = 5.5 V

Figure 7-1 Offset Voltage Distribution Histogram

V_S = 5.5 V, V_CM = V–

Figure 7-3 Input Offset Voltage vs Temperature

Figure 7-5 Offset Voltage vs Common-Mode

V_CM = (V–)

Figure 7-7 Offset Voltage vs Supply Voltage

Figure 7-9 I_B and I_OS vs Common-Mode Voltage

C_L = 10 pF

Figure 7-11 Open-Loop Gain and Phase vs Frequency

V+ = 2.75 V, V– = –2.75 V

R_L = 10 kΩ

Figure 7-13 Open-Loop Gain vs Output Voltage

V+ = 2.75 V, V– = –2.75 V

Figure 7-15 Output Voltage vs Output Current (Claw)

Figure 7-17 PSRR vs Frequency

Figure 7-19 CMRR vs Frequency

Figure 7-21 0.1 Hz to 10 Hz Voltage Noise in Time Domain

V_S = 5.5 V	V_CM = 2.5 V	G = 1
BW = 80 kHz	V_OUT = 0.5 V_RMS

Figure 7-23 THD + N vs Frequency

V_S = 5.5 V	V_CM = 2.5 V	f = 1 kHz
G = 1	BW = 80 kHz

Figure 7-25 THD + N vs Amplitude

Figure 7-27 Quiescent Current vs Supply Voltage

G = 1	V_IN = 100 mVpp

Figure 7-29 Small Signal Overshoot vs Capacitive Load

Figure 7-31 Phase Margin vs Capacitive Load

G = –10	V_IN = 600 mV_PP

Figure 7-33 Overload Recovery

G = 1	V_IN = 4 V_PP	C_L = 10 pF

Figure 7-35 Large-Signal Step Response

G = 1

V_IN = 4 V_PP

C_L = 10 pF

Figure 7-37 Large-Signal Settling Time (Positive)

Figure 7-39 Maximum Output Voltage vs Frequency

Figure 7-41 Shutdown Mode Quiescent Current vs Supply Voltage

Figure 7-43 Amplifier Enable Response

Figure 7-45 Electromagnetic Interference Rejection Ratio Referred to Noninverting Input (EMIRR+) vs Frequency

V_S = 5.5 V, T_A = –40°C to +125°C

Figure 7-2 Offset Voltage Drift Distribution Histogram

V_S = 5.5 V, V_CM = V+

Figure 7-4 Input Offset Voltage vs Temperature

V_CM > (V+) – 1.4 V

Figure 7-6 Offset Voltage vs Common-Mode

Figure 7-8 I_B and I_OS vs Temperature

Figure 7-10 Open-Loop Gain vs Temperature

Figure 7-12 Open-Loop Output Impedance vs Frequency

C_L = 10 pF

Figure 7-14 Closed-Loop Gain vs Frequency

V+ = 0.6 V, V– = –0.6 V

Figure 7-16 Output Voltage vs Output Current (Claw)

V_S = 1.2 V to 5.5 V

Figure 7-18 DC PSRR vs Temperature

Figure 7-20 DC CMRR vs Temperature

Figure 7-22 Input Voltage Noise Spectral Density

V_S = 5.5 V	V_CM = 2.5 V	G = –1
BW = 80 kHz	V_OUT = 0.5 V_RMS

Figure 7-24 THD + N vs Frequency

V_S = 5.5 V	V_CM = 2.5 V	f = 1 kHz
G = –1	BW = 80 kHz

Figure 7-26 THD + N vs Amplitude

Figure 7-28 Quiescent Current vs Temperature

G = –1	V_IN = 100 mVpp

Figure 7-30 Small Signal Overshoot vs Capacitive Load

G = 1	V_IN = 6 V_PP

Figure 7-32 No Phase Reversal

G = 1	V_IN = 20 mV_PP	C_L = 10 pF

Figure 7-34 Small-Signal Step Response

G = 1

V_IN = 4 V_PP

C_L = 10 pF

Figure 7-36 Large-Signal Settling Time (Negative)

G = –1	V_IN = 4 V_PP	C_L = 10 pF

Figure 7-38 Large-Signal Step Response

Figure 7-40 Short-Circuit Current vs Temperature

Figure 7-42 Shutdown Mode Quiescent Current vs Temperature

Figure 7-44 Amplifier Disable Response

Figure 7-46 Channel Separation