SBOS836G March   2020  – March 2022 TLV9041 , TLV9042 , TLV9044

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information for Single Channel
    5. 7.5 Thermal Information for Dual Channel
    6. 7.6 Thermal Information for Quad Channel
    7. 7.7 Electrical Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Operating Voltage
      2. 8.3.2  Rail-to-Rail Input
      3. 8.3.3  Rail-to-Rail Output
      4. 8.3.4  Common-Mode Rejection Ratio (CMRR)
      5. 8.3.5  Capacitive Load and Stability
      6. 8.3.6  Overload Recovery
      7. 8.3.7  EMI Rejection
      8. 8.3.8  Electrical Overstress
      9. 8.3.9  Input and ESD Protection
      10. 8.3.10 Shutdown Function
      11. 8.3.11 Packages With an Exposed Thermal Pad
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 TLV904x Low-Side, Current Sensing Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4.     Trademarks
    5. 12.4 Electrostatic Discharge Caution
    6. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.7 Electrical Characteristics

For VS = (V+) – (V–) = 1.2 V to 5.5 V (±0.6 V to ±2.75 V) at TA = 25°C, RL = 100 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2, unless otherwise noted.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
VOS Input offset voltage ±0.6 ±2.25 mV
TA = –40°C to 125°C ±2.5
dVOS/dT Input offset voltage drift TA = –40°C to 125°C ±0.8 µV/℃
PSRR Input offset voltage versus power supply VS = ±0.6 V to ±2.75 V , VCM = V– ±20 ±100 µV/V
Channel separation f = 10 kHz ±5.6 µV/V
INPUT BIAS CURRENT
IB Input bias current (1) ±1 ±12 pA
IOS Input offset current (1) ±0.5 ±10 pA
NOISE
EN Input voltage noise f  = 0.1 to 10 Hz   6.5 μVPP
eN Input voltage noise density f = 100 Hz 85 nV/√Hz
f = 1 kHz   66  
f = 10 kHz   64  
iN Input current noise (2) f = 1 kHz   20   fA/√Hz
INPUT VOLTAGE RANGE
VCM Common-mode voltage range (V–) (V+) V
CMRR Common-mode rejection ratio (V–) < VCM < (V+) – 0.7 V, VS = 1.2 V TA = –40°C to 125°C 60 77 dB
(V–) < VCM < (V+) – 0.7 V, VS = 5.5 V  75 89
(V–) < VCM < (V+), VS = 1.2 V  60
(V–) < VCM < (V+), VS = 5.5 V  57 72
INPUT IMPEDANCE
ZID Differential 80 || 1.4 GΩ || pF
ZICM Common-mode 100 || 0.5 GΩ || pF
OPEN-LOOP GAIN
AOL Open-loop voltage gain VS = 1.2 V, (V–) + 0.2 V < VO < (V+) – 0.2 V,
RL = 10 kΩ to VS / 2		 TA = –40°C to 125°C 98 dB
VS = 5.5 V, (V–) + 0.2 V < VO < (V+) – 0.2 V,
RL = 10 kΩ to VS / 2		 125
VS = 1.2 V, (V–) + 0.1 V < VO < (V+) – 0.1 V,
RL = 100 kΩ to VS / 2		 105
VS = 5.5 V, (V–) + 0.1 V < VO < (V+) – 0.1 V,
RL = 100 kΩ to VS / 2		 107 130
FREQUENCY RESPONSE
THD+N Total harmonic distortion + noise (3) VS = 5.5 V, VCM = 2.75 V, VO = 1 VRMS, G = +1, f = 1 kHz,
RL = 100 kΩ to VS / 2		 0.013 %
GBW Gain-bandwidth product RL = 1 MΩ connected to VS/2 350 kHz
SR Slew rate VS = 5.5 V, G = +1, CL = 10 pF 0.2 V/μs
tS Settling time To 0.1%, VS = 5.5 V, VSTEP = 4 V, G = +1, CL = 10 pF 25 μs
To 0.1%, VS = 5.5 V, VSTEP = 2 V, G = +1, CL = 10 pF 22
To 0.01%, VS = 5.5 V, VSTEP = 4 V, G = +1, CL = 10 pF 35
To 0.01%, VS = 5.5 V, VSTEP = 2 V, G = +1, CL = 10 pF 30
Phase margin G = +1, RL = 100 kΩ connected to VS/2, CL = 10 pF 65 °
Overload recovery time VIN  × gain > VS 13 μs
EMIRR Electro-magnetic interference rejection ratio f = 1 GHz, VIN_EMIRR = 100 mV 70 dB
OUTPUT
  Voltage output swing from rail Positive rail headroom VS = 1.2 V,
RL = 100 kΩ to VS / 2		   0.75 7 mV
VS = 5.5 V,
RL = 10 kΩ to VS / 2		   10 21
VS = 5.5 V,
RL = 100 kΩ to VS / 2		   1 8
Negative rail headroom VS = 1.2 V,
RL = 100 kΩ to VS / 2		   0.75 5
VS = 5.5 V,
RL = 10 kΩ to VS / 2		   10 21
VS = 5.5 V,
RL = 100 kΩ to VS / 2		   1 8
ISC Short-circuit current (4) VS = 5.5 V ±40 mA
ZO Open-loop output impedance f = 10 kHz 7500 Ω
POWER SUPPLY
IQ Quiescent current per amplifier VS = 5.5 V, IO = 0 A 10 13 µA
TA = –40°C to 125°C 13.5
IQ Quiescent current per amplifier VS = 5.5 V, IO = 0 A, For TLV9041UIDBVR Only 10 13.5 µA
TA = –40°C to 125°C 14 µA
SHUTDOWN
IQSD Quiescent current per amplifier All amplifiers disabled, SHDN = V– 75 200 nA
ZSHDN Output impedance during shutdown Amplifier disabled 43 || 11.5 GΩ || pF
VIH Logic high threshold voltage (amplifier enabled) (V–) + 1 V V
VIL Logic low threshold voltage (amplifier disabled) (V–) + 0.2 V V
tON Amplifier enable time (full shutdown) (5) (6) G = +1, VCM = VS / 2, VO = 0.9 × VS / 2, RL connected to V– 160 µs
Amplifier enable time (partial shutdown) (5) (6) G = +1, VCM = VS / 2, VO = 0.9 × VS / 2, RL connected to V– 120
tOFF Amplifier disable time (5) G = +1, VCM = VS / 2, VO = 0.1 × VS / 2, RL connected to V– 10 µs
SHDN pin input bias current (per pin) (V+) ≥ SHDN ≥ (V–) + 1 V 100 pA
(V–) ≤ SHDN ≤ (V–) + 0.2 V 50
(1) Max IB and IOS limits are specified based on characterization results. Input differential voltages greater than 2.5V can cause increased IB
(2) Typical input current noise data is specified based on design simulation results
(3) Third-order filter; bandwidth = 80 kHz at –3 dB.
(4) Short circuit current is average of sourcing and sinking short circuit currents
(5) Disable time (tOFF) and enable time (tON) are defined as the time interval between the 50% point of the signal applied to the SHDN pin and the point at which the output voltage reaches the 10% (disable) or 90% (enable) level.
(6) Full shutdown refers to the dual TLV9042S having both channels 1 and 2 disabled (SHDN1 = SHDN2 = V–) and the quad TLV9044S having all channels 1 to 4 disabled (SHDN12 = SHDN34 = V–). For partial shutdown, only one SHDN pin is exercised; in this mode, the internal biasing circuitry remains operational and the enable time is shorter.