SBOSAH8B February   2024  – May 2024 TLV9051-Q1 , TLV9052-Q1

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information for Single Channel
    5. 5.5 Thermal Information for Dual Channel
    6. 5.6 Thermal Information for Quad Channel
    7. 5.7 Electrical Characteristics: VS (Total Supply Voltage) = (V+) – (V–) = 1.8V to 5.5V
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Operating Voltage
      2. 6.3.2 Rail-to-Rail Input
      3. 6.3.3 Rail-to-Rail Output
      4. 6.3.4 EMI Rejection
      5. 6.3.5 Overload Recovery
      6. 6.3.6 Electrical Overstress
      7. 6.3.7 Input Protection
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Low-Side Current Sense Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curve
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 TINA-TI (Free Software Download)
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DBV|5
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Pin Configuration and Functions

TLV9051-Q1 TLV9052-Q1 TLV9051-Q1 DBV Package,5-Pin SOT-23(Top View)Figure 4-1 TLV9051-Q1 DBV Package,
5-Pin SOT-23
(Top View)
TLV9051-Q1 TLV9052-Q1 TLV9051-Q1 DCK Package,5-Pin SC70(Top View)Figure 4-2 TLV9051-Q1 DCK Package,
5-Pin SC70
(Top View)
Table 4-1 Pin Functions: TLV9051-Q1
PIN TYPE(1) DESCRIPTION
NAME SOT-23 SC-70
IN– 4 3 I Inverting input
IN+ 3 1 I Noninverting input
OUT 1 4 O Output
V– 2 2 — Negative (low) supply or ground (for single-supply operation)
V+ 5 5 — Positive (high) supply
(1) I = input, O = output
TLV9051-Q1 TLV9052-Q1 TLV9052-Q1 D, DGK, PW Packages,8-Pin SOIC, VSSOP, TSSOP(Top View)Figure 4-3 TLV9052-Q1 D, DGK, PW Packages,
8-Pin SOIC, VSSOP, TSSOP
(Top View)
Table 4-2 Pin Functions: TLV9052-Q1
PINTYPE(1)DESCRIPTION
NAMENO.
IN1–2IInverting input, channel 1
IN1+3INoninverting input, channel 1
IN2–6IInverting input, channel 2
IN2+5INoninverting input, channel 2
OUT11OOutput, channel 1
OUT27OOutput, channel 2
V–4—Negative (low) supply or ground (for single-supply operation)
V+8—Positive (high) supply
(1) I = input, O = output
TLV9051-Q1 TLV9052-Q1 TLV9054-Q1 D, PW Packages,14-Pin SOIC, TSSOP(Top View)Figure 4-4 TLV9054-Q1 D, PW Packages,
14-Pin SOIC, TSSOP
(Top View)
Table 4-3 Pin Functions: TLV9054-Q1
PIN TYPE(1) DESCRIPTION
NAME NO.
IN1– 2 I Inverting input, channel 1
IN1+ 3 I Noninverting input, channel 1
IN2– 6 I Inverting input, channel 2
IN2+ 5 I Noninverting input, channel 2
IN3– 9 I Inverting input, channel 3
IN3+ 10 I Noninverting input, channel 3
IN4– 13 I Inverting input, channel 4
IN4+ 12 I Noninverting input, channel 4
OUT1 1 O Output, channel 1
OUT2 7 O Output, channel 2
OUT3 8 O Output, channel 3
OUT4 14 O Output, channel 4
V– 11 — Negative (low) supply or ground (for single-supply operation)
V+ 4 — Positive (high) supply
(1) I = input, O = output