SBOS943E February   2019  – August 2021 TLV9101 , TLV9102 , TLV9104

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information for Single Channel
    5. 6.5 Thermal Information for Dual Channel
    6. 6.6 Thermal Information for Quad Channel
    7. 6.7 Electrical Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  EMI Rejection
      2. 7.3.2  Phase Reversal Protection
      3. 7.3.3  Thermal Protection
      4. 7.3.4  Capacitive Load and Stability
      5. 7.3.5  Common-Mode Voltage Range
      6. 7.3.6  Electrical Overstress
      7. 7.3.7  Overload Recovery
      8. 7.3.8  Typical Specifications and Distributions
      9. 7.3.9  Packages With an Exposed Thermal Pad
      10. 7.3.10 Shutdown
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 High Voltage Precision Comparator
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 TINA-TI (Free Software Download)
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

Figure 5-1 TLV9101 DBV Package
5-Pin SOT-23
Top View
Package is preview only.
Figure 5-2 TLV9101 DCK and DRL Package(A)
5-Pin SC70 and SOT-553
Top View
Table 5-1 Pin Functions: TLV9101
PIN I/O DESCRIPTION
NAME DBV DCK and DRL
+IN 3 1 I Noninverting input
–IN 4 3 I Inverting input
OUT 1 4 O Output
V+ 5 5 — Positive (highest) power supply
V– 2 2 — Negative (lowest) power supply
GUID-20200923-CA0I-FHFJ-MWVW-NKKCPKSQXHZR-low.gif Figure 5-3 TLV9101S DBV Package
6-Pin SOT-23
Top View
Table 5-2 Pin Functions: TLV9101S
PIN I/O DESCRIPTION
NAME NO.
IN+ 3 I Noninverting input
IN– 4 I Inverting input
OUT 1 O Output
SHDN 5 I Shutdown: low = amplifier enabled, high = amplifier disabled. See Section 7.3.10 for more information.
V+ 6 — Positive (highest) power supply
V– 2 — Negative (lowest) power supply
Figure 5-4 TLV9102 D, DDF, DGK, and PW Package
8-Pin SOIC, SOT-23, TSSOP, and VSSOP
Top View
Connect thermal pad to V–. See Section 7.3.9 for more information.
Figure 5-5 TLV9102 DSG Package(A)
8-Pin WSON With Exposed Thermal Pad
Top View
Table 5-3 Pin Functions: TLV9102
PIN I/O DESCRIPTION
NAME NO.
IN1+ 3 I Noninverting input, channel 1
IN1– 2 I Inverting input, channel 1
IN2+ 5 I Noninverting input, channel 2
IN2– 6 I Inverting input, channel 2
OUT1 1 O Output, channel 1
OUT2 7 O Output, channel 2
V+ 8 — Positive (highest) power supply
V– 4 — Negative (lowest) power supply
GUID-20200923-CA0I-CZRZ-PLL2-RNNNTWJKQ9LL-low.gifFigure 5-6 TLV9102S DGS Package
10-Pin VSSOP
Top View
GUID-20200923-CA0I-SVLD-BBNV-0CGFTWNFSL2P-low.gifFigure 5-7 TLV9102S RUG Package
10-Pin X2QFN
Top View
Table 5-4 Pin Functions: TLV9102S
PIN I/O DESCRIPTION
NAME VSSOP X2QFN
IN1+ 3 10 I Noninverting input, channel 1
IN1– 2 9 I Inverting input, channel 1
IN2+ 7 4 I Noninverting input, channel 2
IN2– 8 5 I Inverting input, channel 2
OUT1 1 8 O Output, channel 1
OUT2 9 6 O Output, channel 2
SHDN1 5 2 I Shutdown, channel 1: low = amplifier enabled, high = amplifier disabled. See Section 7.3.10 for more information.
SHDN2 6 3 I Shutdown, channel 2: low = amplifier enabled, high = amplifier disabled. See Section 7.3.10 for more information.
V+ 10 7 — Positive (highest) power supply
V– 4 1 — Negative (lowest) power supply
Figure 5-8 TLV9104 D and PW Package
14-Pin SOIC and TSSOP
Top View
Figure 5-10 TLV9104 RUC Package
14-Pin WQFN With Exposed Thermal Pad
Top View
Connect thermal pad to V–. See Section 7.3.9 for more information.
Figure 5-9 TLV9104 RTE Package(A)
16-Pin WQFN With Exposed Thermal Pad
Top View
Table 5-5 Pin Functions: TLV9104
PIN I/O DESCRIPTION
NAME SOIC and TSSOP WQFN X2QFN
IN1+ 3 1 2 I Noninverting input, channel 1
IN1– 2 16 1 I Inverting input, channel 1
IN2+ 5 3 4 I Noninverting input, channel 2
IN2– 6 4 5 I Inverting input, channel 2
IN3+ 10 10 9 I Noninverting input, channel 3
IN3– 9 9 8 I Inverting input, channel 3
IN4+ 12 12 11 I Noninverting input, channel 4
IN4– 13 13 12 I Inverting input, channel 4
NC — 6, 7 — — Do not connect
OUT1 1 15 14 O Output, channel 1
OUT2 7 5 6 O Output, channel 2
OUT3 8 8 7 O Output, channel 3
OUT4 14 14 13 O Output, channel 4
V+ 4 2 3 — Positive (highest) power supply
V– 11 11 10 — Negative (lowest) power supply
GUID-20200923-CA0I-TMPB-VDHW-J2ZFNKT9BLB7-low.gif
Connect thermal pad to V–. See Section 7.3.9 for more information.
Figure 5-11 TLV9104S RTE Package(A)
16-Pin WQFN With Exposed Thermal Pad
Top View
Table 5-6 Pin Functions: TLV9104S
PIN I/O DESCRIPTION
NAME NO.
IN1+ 1 I Noninverting input, channel 1
IN1– 16 I Inverting input, channel 1
IN2+ 3 I Noninverting input, channel 2
IN2– 4 I Inverting input, channel 2
IN3+ 10 I Noninverting input, channel 3
IN3– 9 I Inverting input, channel 3
IN4+ 12 I Noninverting input, channel 4
IN4– 13 I Inverting input, channel 4
OUT1 15 O Output, channel 1
OUT2 5 O Output, channel 2
OUT3 8 O Output, channel 3
OUT4 14 O Output, channel 4
SHDN12 6 I Shutdown, channels 1 and 2: low = amplifiers enabled, high = amplifiers disabled. See Section 7.3.10 for more information.
SHDN34 7 I Shutdown, channels 3 and 4: low = amplifiers enabled, high = amplifiers disabled. See Section 7.3.10 for more information.
V+ 2 — Positive (highest) power supply
V– 11 — Negative (lowest) power supply