The TLV910x family (TLV9101, TLV9102, and TLV9104) is a family of 16-V general purpose operational amplifiers. This family offers excellent DC precision and AC performance, including rail-to-rail input/output, low offset (±300 µV, typ), low offset drift (±0.6 µV/°C, typ), and 1.1-MHz bandwidth.
Wide differential and common-mode input-voltage range, high output current (±80 mA, typ), high slew rate (4.5 V/µs, typ), low power operation (115 µA, typ) and shutdown functionality make the TLV910x a robust, low-power, high-performance operational amplifier for industrial applications.
The TLV910x family of op amps is available in micro-size packages, as well as standard packages, and is specified from –40°C to 125°C.
PART NUMBER (1) | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TLV9101 | SOT-23 (5) | 2.90 mm × 1.60 mm |
SOT-23 (6) | 2.90 mm × 1.60 mm | |
SC70 (5) | 2.00 mm × 1.25 mm | |
SOT-553 (5)(2) | 1.60 mm × 1.20 mm | |
TLV9102 | SOIC (8) | 4.90 mm × 3.90 mm |
SOT-23 (8) | 2.90 mm × 1.60 mm | |
TSSOP (8) | 3.00 mm × 4.40 mm | |
VSSOP (8) | 3.00 mm × 3.00 mm | |
VSSOP (10) | 3.00 mm × 3.00 mm | |
WSON (8) | 2.00 mm × 2.00 mm | |
X2QFN (10) | 1.50 mm × 1.50 mm | |
TLV9104 | SOIC (14) | 8.65 mm × 3.90 mm |
TSSOP (14) | 5.00 mm × 4.40 mm | |
WQFN (16) | 3.00 mm × 3.00 mm | |
X2QFN (14) | 2.00 mm × 2.00 mm |
Changes from Revision D (June 2021) to Revision E (August 2021)
Changes from Revision C (May 2020) to Revision D (June 2021)
Changes from Revision B (May 2020) to Revision C (May 2020)
Changes from Revision A (April 2019) to Revision B (May 2020)
PIN | I/O | DESCRIPTION | ||
---|---|---|---|---|
NAME | DBV | DCK and DRL | ||
+IN | 3 | 1 | I | Noninverting input |
–IN | 4 | 3 | I | Inverting input |
OUT | 1 | 4 | O | Output |
V+ | 5 | 5 | — | Positive (highest) power supply |
V– | 2 | 2 | — | Negative (lowest) power supply |
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
IN+ | 3 | I | Noninverting input |
IN– | 4 | I | Inverting input |
OUT | 1 | O | Output |
SHDN | 5 | I | Shutdown: low = amplifier enabled, high = amplifier disabled. See Section 7.3.10 for more information. |
V+ | 6 | — | Positive (highest) power supply |
V– | 2 | — | Negative (lowest) power supply |
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
IN1+ | 3 | I | Noninverting input, channel 1 |
IN1– | 2 | I | Inverting input, channel 1 |
IN2+ | 5 | I | Noninverting input, channel 2 |
IN2– | 6 | I | Inverting input, channel 2 |
OUT1 | 1 | O | Output, channel 1 |
OUT2 | 7 | O | Output, channel 2 |
V+ | 8 | — | Positive (highest) power supply |
V– | 4 | — | Negative (lowest) power supply |
PIN | I/O | DESCRIPTION | ||
---|---|---|---|---|
NAME | VSSOP | X2QFN | ||
IN1+ | 3 | 10 | I | Noninverting input, channel 1 |
IN1– | 2 | 9 | I | Inverting input, channel 1 |
IN2+ | 7 | 4 | I | Noninverting input, channel 2 |
IN2– | 8 | 5 | I | Inverting input, channel 2 |
OUT1 | 1 | 8 | O | Output, channel 1 |
OUT2 | 9 | 6 | O | Output, channel 2 |
SHDN1 | 5 | 2 | I | Shutdown, channel 1: low = amplifier enabled, high = amplifier disabled. See Section 7.3.10 for more information. |
SHDN2 | 6 | 3 | I | Shutdown, channel 2: low = amplifier enabled, high = amplifier disabled. See Section 7.3.10 for more information. |
V+ | 10 | 7 | — | Positive (highest) power supply |
V– | 4 | 1 | — | Negative (lowest) power supply |
PIN | I/O | DESCRIPTION | |||
---|---|---|---|---|---|
NAME | SOIC and TSSOP | WQFN | X2QFN | ||
IN1+ | 3 | 1 | 2 | I | Noninverting input, channel 1 |
IN1– | 2 | 16 | 1 | I | Inverting input, channel 1 |
IN2+ | 5 | 3 | 4 | I | Noninverting input, channel 2 |
IN2– | 6 | 4 | 5 | I | Inverting input, channel 2 |
IN3+ | 10 | 10 | 9 | I | Noninverting input, channel 3 |
IN3– | 9 | 9 | 8 | I | Inverting input, channel 3 |
IN4+ | 12 | 12 | 11 | I | Noninverting input, channel 4 |
IN4– | 13 | 13 | 12 | I | Inverting input, channel 4 |
NC | — | 6, 7 | — | — | Do not connect |
OUT1 | 1 | 15 | 14 | O | Output, channel 1 |
OUT2 | 7 | 5 | 6 | O | Output, channel 2 |
OUT3 | 8 | 8 | 7 | O | Output, channel 3 |
OUT4 | 14 | 14 | 13 | O | Output, channel 4 |
V+ | 4 | 2 | 3 | — | Positive (highest) power supply |
V– | 11 | 11 | 10 | — | Negative (lowest) power supply |
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
IN1+ | 1 | I | Noninverting input, channel 1 |
IN1– | 16 | I | Inverting input, channel 1 |
IN2+ | 3 | I | Noninverting input, channel 2 |
IN2– | 4 | I | Inverting input, channel 2 |
IN3+ | 10 | I | Noninverting input, channel 3 |
IN3– | 9 | I | Inverting input, channel 3 |
IN4+ | 12 | I | Noninverting input, channel 4 |
IN4– | 13 | I | Inverting input, channel 4 |
OUT1 | 15 | O | Output, channel 1 |
OUT2 | 5 | O | Output, channel 2 |
OUT3 | 8 | O | Output, channel 3 |
OUT4 | 14 | O | Output, channel 4 |
SHDN12 | 6 | I | Shutdown, channels 1 and 2: low = amplifiers enabled, high = amplifiers disabled. See Section 7.3.10 for more information. |
SHDN34 | 7 | I | Shutdown, channels 3 and 4: low = amplifiers enabled, high = amplifiers disabled. See Section 7.3.10 for more information. |
V+ | 2 | — | Positive (highest) power supply |
V– | 11 | — | Negative (lowest) power supply |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Supply voltage, VS = (V+) – (V–) | 0 | 20 | V | |
Signal input pins | Common-mode voltage(3) | (V–) – 0.5 | (V+) + 0.5 | V |
Differential voltage(3) | VS + 0.2 | V | ||
Current(3) | –10 | 10 | mA | |
Shutdown pin voltage | V– | V+ | V | |
Output short-circuit(2) | Continuous | |||
Operating ambient temperature, TA | –55 | 150 | °C | |
Junction temperature, TJ | 150 | °C | ||
Storage temperature, Tstg | –65 | 150 | °C |
VALUE | UNIT | ||||
---|---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V | |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±1000 |
MIN | MAX | UNIT | ||
---|---|---|---|---|
VS | Supply voltage, (V+) – (V–) | 2.7 | 16 | V |
VI | Input voltage range | (V–) – 0.2 | (V+) + 0.2 | V |
VIH | High level input voltage at shutdown pin (amplifier disabled) | (V–) + 1.1 | V+ | V |
VIL | Low level input voltage at shutdown pin (amplifier enabled) | V– | (V–) + 0.2 | V |
TA | Specified temperature | –40 | 125 | °C |
THERMAL METRIC(1) | TLV9101, TLV9101S | UNIT | ||||
---|---|---|---|---|---|---|
DBV (SOT-23) |
DCK (SC70) |
DRL(2)
(SOT-553) |
||||
5 PINS | 6 PINS | 5 PINS | 5 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 192.2 | 174.6 | 204.7 | TBD | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 113.7 | 113.5 | 116.6 | TBD | °C/W |
RθJB | Junction-to-board thermal resistance | 60.6 | 55.9 | 51.9 | TBD | °C/W |
ψJT | Junction-to-top characterization parameter | 37.4 | 39.7 | 24.9 | TBD | °C/W |
ψJB | Junction-to-board characterization parameter | 60.4 | 55.7 | 51.6 | TBD | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | N/A | N/A | N/A | TBD | °C/W |
THERMAL METRIC(1) | TLV9102, TLV9102S | UNIT | |||||||
---|---|---|---|---|---|---|---|---|---|
D (SOIC) |
DDF (SOT-23-8) |
DGK (VSSOP) |
DGS (VSSOP) |
DSG (WSON) |
PW (TSSOP) |
RUG (X2QFN) |
|||
8 PINS | 8 PINS | 8 PINS | 10 PINS | 8 PINS | 8 PINS | 10 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 138.7 | 150.4 | 189.3 | 152.2 | 81.6 | 188.4 | 149.6 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 78.7 | 85.6 | 75.8 | 67.3 | 101.6 | 77.1 | 58.3 | °C/W |
RθJB | Junction-to-board thermal resistance | 82.2 |
70.0 |
111.0 | 95.5 | 48.3 | 119.1 | 77.7 | °C/W |
ψJT | Junction-to-top characterization parameter | 27.8 | 8.1 | 15.4 | 67.9 | 6.0 | 14.2 | 1.3 | °C/W |
ψJB | Junction-to-board characterization parameter | 81.4 | 69.6 | 109.3 | 94.3 | 48.3 | 117.4 | 77.5 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | N/A | N/A | N/A | N/A | 22.8 | N/A | N/A | °C/W |
THERMAL METRIC(1) | TLV9104, TLV9104S | UNIT | ||||
---|---|---|---|---|---|---|
D (SOIC) |
PW (TSSOP) |
RTE (WQFN) |
RUC (WQFN) |
|||
14 PINS | 14 PINS | 16 PINS | 14 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 105.2 | 134.7 | 53.5 | 143.0 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 61.2 | 55.0 | 58.3 | 46.4 | °C/W |
RθJB | Junction-to-board thermal resistance | 61.1 | 79.0 | 28.6 | 81.8 | °C/W |
ψJT | Junction-to-top characterization parameter | 21.4 | 9.2 | 2.1 | 1.0 | °C/W |
ψJB | Junction-to-board characterization parameter | 60.7 | 78.1 | 28.6 | 81.5 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | N/A | N/A | 12.6 | N/A | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
OFFSET VOLTAGE | |||||||
VOS | Input offset voltage | VCM = V– | ±0.3 | ±1.5 | mV | ||
TA = –40°C to 125°C | ±1.75 | ||||||
dVOS/dT | Input offset voltage drift | TA = –40°C to 125°C | ±0.6 | µV/℃ | |||
PSRR | Input offset voltage versus power supply | VCM = V– | TA = –40°C to 125°C | ±0.1 | ±0.7 | µV/V | |
Channel separation | f = 0 Hz | 5 | µV/V | ||||
INPUT BIAS CURRENT | |||||||
IB | Input bias current | ±10 | pA | ||||
IOS | Input offset current | ±5 | pA | ||||
NOISE | |||||||
EN | Input voltage noise | f = 0.1 Hz to 10 Hz | 6 | µVPP | |||
1 | µVRMS | ||||||
eN | Input voltage noise density | f = 1 kHz | 30 | nV/√Hz | |||
f = 10 kHz | 28 | ||||||
iN | Input current noise | f = 1 kHz | 2 | fA/√Hz | |||
INPUT VOLTAGE RANGE | |||||||
VCM | Common-mode voltage range | (V–) – 0.2 | (V+) + 0.2 | V | |||
CMRR | Common-mode rejection ratio | VS = 16 V, (V–) – 0.1 V < VCM < (V+) – 2 V (Main input pair) | TA = –40°C to 125°C | 90 | 110 | dB | |
VS = 4 V, (V–) – 0.1 V < VCM < (V+) – 2 V (Main input pair) | 75 | 95 | |||||
VS = 2.7 – 16 V, (V+) – 1 V < VCM < (V+) + 0.1 V (Aux input pair) | 80 | ||||||
(V+) – 2 V < VCM < (V+) – 1 V | See Offset Voltage (Transition Region) in the Typical Characteristics section | ||||||
INPUT CAPACITANCE | |||||||
ZID | Differential | 100 || 3 | MΩ || pF | ||||
ZICM | Common-mode | 6 || 1 | TΩ || pF | ||||
OPEN-LOOP GAIN | |||||||
AOL | Open-loop voltage gain | VS = 16 V, VCM = V– (V–) + 0.1 V < VO < (V+) – 0.1 V |
TA = –40°C to 125°C | 115 | 135 | dB | |
VS = 4 V, VCM = V– (V–) + 0.1 V < VO < (V+) – 0.1 V |
104 | 125 | dB | ||||
FREQUENCY RESPONSE | |||||||
GBW | Gain-bandwidth product | 1.1 | MHz | ||||
SR | Slew rate | VS = 16 V, G = +1, CL = 20 pF | 4.5 | V/µs | |||
tS | Settling time | To 0.1%, VS = 16 V, VSTEP = 10 V, G = +1, CL = 20 pF | 4 | µs | |||
To 0.1%, VS = 16 V, VSTEP = 2 V, G = +1, CL = 20 pF | 2 | ||||||
To 0.01%, VS = 16 V, VSTEP = 10 V, G = +1, CL = 20 pF | 5 | ||||||
To 0.01%, VS = 16 V, VSTEP = 2 V, G = +1, CL = 20 pF | 3 | ||||||
Phase margin | G = +1, RL = 10 kΩ, CL = 20 pF | 60 | ° | ||||
Overload recovery time | VIN × gain > VS | 600 | ns | ||||
THD+N | Total harmonic distortion + noise | VS = 16 V, VO = 1 VRMS, G = -1, f = 1 kHz | 0.0028% | ||||
OUTPUT | |||||||
Voltage output swing from rail | Positive and negative rail headroom | VS = 16 V, RL = no load | 3 | mV | |||
VS = 16 V, RL = 10 kΩ | 45 | 60 | |||||
VS = 16 V, RL = 2 kΩ | 200 | 300 | |||||
VS = 2.7 V, RL = no load | 1 | ||||||
VS = 2.7 V, RL = 10 kΩ | 5 | 20 | |||||
VS = 2.7 V, RL = 2 kΩ | 25 | 50 | |||||
ISC | Short-circuit current | ±80 | mA | ||||
CLOAD | Capacitive load drive | See Small-Signal Overshoot vs Capacitive Load in the Typical Characteristics section | |||||
ZO | Open-loop output impedance | f = 1 MHz, IO = 0 A | 600 | Ω | |||
POWER SUPPLY | |||||||
IQ | Quiescent current per amplifier | IO = 0 A | 115 | 150 | µA | ||
TA = –40°C to 125°C | 160 | ||||||
SHUTDOWN | |||||||
IQSD | Quiescent current per amplifier | VS = 2.7 V to 16 V, all amplifiers disabled, SHDN = V+ | 20 | 30 | µA | ||
ZSHDN | Output impedance during shutdown | VS = 2.7 V to 16 V, amplifier disabled, SHDN = V+ | 10 || 12 | GΩ || pF | |||
VIH | Logic high threshold voltage (amplifier disabled) | For valid input high, the SHDN pin voltage should be greater than the maximum threshold but less than or equal to V+ | (V–) + 0.8 | (V–) + 1.1 | V | ||
VIL | Logic low threshold voltage (amplifier enabled) | For valid input low, the SHDN pin voltage should be less than the minimum threshold but greater than or equal to V– | (V–) + 0.2 | (V–) + 0.8 | V | ||
tON | Amplifier enable time (1) | G = +1, VCM = V–, VO = 0.1 × VS / 2 | 11 | µs | |||
tOFF | Amplifier disable time (1) | VCM = V–, VO = VS / 2 | 2.5 | µs | |||
SHDN pin input bias current (per pin) | VS = 2.7 V to 16 V, (V–) + 20 V ≥ SHDN ≥ (V–) + 0.9 V | 500 | nA | ||||
VS = 2.7 V to 16 V, (V–) ≤ SHDN ≤ (V–) + 0.7 V | 150 |
at TA = 25°C, VS = ±8 V, VCM = VS / 2, RLOAD = 10 kΩ connected to VS / 2, and CL = 100 pF (unless otherwise noted)
Distribution from 13, 481 amplifiers; TA = 25°C |
VCM = V+ | ||
Each color represents one sample device. |
TA = 25°C | ||
Each color represents one sample device. |
TA = 125°C | ||
Each color represents one sample device. |
VCM = V– | ||
Each color represents one sample device. |
VS = 5 V, RL connected to V+ |
f = 0 Hz |
BW = 80 kHz, VOUT = 3.5 VRMS |
G = –1, 100-mV output step |
G = –1, 100-mV output step |
G = –10 |
CL = 20 pF, G = 1, 20-mV step response |
CL = 20 pF, G = 1 |
CL = 10 pF, G = –1 |
Distribution from 175 amplifiers |
VCM = V– | ||
Each color represents one sample device. |
TA = 25°C | ||
Each color represents one sample device. |
TA = –40°C | ||
Each color represents one sample device. |
CLOAD = 15 pF | ||
VS = 5 V, RL connected to V– |
f = 0 Hz |
BW = 80 kHz, f = 1 kHz |
G = 1, 100-mV output step |
G = –10 |
RL = 1 kΩ, CL = 20 pF, G = –1, 10-mV step response |
CL = 20 pF, G = 1 |
The TLV910x family (TLV9101, TLV9102, and TLV9104) is a family of 16-V general purpose operational amplifiers.
These devices offer excellent DC precision and AC performance, including rail-to-rail input/output, low offset (±300 µV, typ), low offset drift (±0.6 µV/°C, typ), and 1.1-MHz bandwidth.
Wide differential and common-mode input-voltage range, high output current (±80 mA), high slew rate (4.5 V/µs), low power operation (120 µA, typ), and shutdown functionality make the TLV910x a robust, low-power, high-performance operational amplifier for industrial applications.
The TLV910x uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI from sources such as wireless communications and densely-populated boards with a mix of analog signal chain and digital components. EMI immunity can be improved with circuit design techniques; the TLV910x benefits from these design improvements. Texas Instruments has developed the ability to accurately measure and quantify the immunity of an operational amplifier over a broad frequency spectrum extending from 10 MHz to 6 GHz. Figure 7-1 shows the results of this testing on the TLV910x. Table 7-1 shows the EMIRR IN+ values for the TLV910x at particular frequencies commonly encountered in real-world applications. Table 7-1 lists applications that can be centered on or operated near the particular frequency shown. The EMI Rejection Ratio of Operational Amplifiers application report contains detailed information on the topic of EMIRR performance as it relates to op amps and is available for download from www.ti.com.
FREQUENCY | APPLICATION OR ALLOCATION | EMIRR IN+ |
---|---|---|
400 MHz | Mobile radio, mobile satellite, space operation, weather, radar, ultra-high frequency (UHF) applications | 59.5 dB |
900 MHz | Global system for mobile communications (GSM) applications, radio communication, navigation, GPS (to 1.6 GHz), GSM, aeronautical mobile, UHF applications | 68.9 dB |
1.8 GHz | GSM applications, mobile personal communications, broadband, satellite, L-band (1 GHz to 2 GHz) | 77.8 dB |
2.4 GHz | 802.11b, 802.11g, 802.11n, Bluetooth®, mobile personal communications, industrial, scientific and medical (ISM) radio band, amateur radio and satellite, S-band (2 GHz to 4 GHz) | 78.0 dB |
3.6 GHz | Radiolocation, aero communication and navigation, satellite, mobile, S-band | 88.8 dB |
5 GHz | 802.11a, 802.11n, aero communication and navigation, mobile communication, space and satellite operation, C-band (4 GHz to 8 GHz) | 87.6 dB |
The TLV910x family has internal phase-reversal protection. Many op amps exhibit a phase reversal when the input is driven beyond its linear common-mode range. This condition is most often encountered in noninverting circuits when the input is driven beyond the specified common-mode voltage range, causing the output to reverse into the opposite rail. The TLV910x is a rail-to-rail input op amp; therefore, the common-mode range can extend up to the rails. Input signals beyond the rails do not cause phase reversal; instead, the output limits into the appropriate rail. This performance is shown in Figure 7-2.
The internal power dissipation of any amplifier causes its internal (junction) temperature to rise. This phenomenon is called self heating. The absolute maximum junction temperature of the TLV910x is 150°C. Exceeding this temperature causes damage to the device. The TLV910x has a thermal protection feature that prevents damage from self heating. The protection works by monitoring the temperature of the device and turning off the op amp output drive for temperatures above 140°C. Figure 7-3 shows an application example for the TLV9101 that has significant self heating (154°C) because of its power dissipation (0.39 W). Thermal calculations indicate that for an ambient temperature of 100°C, the device junction temperature must reach 154°C. The actual device, however, turns off the output drive to maintain a safe junction temperature. Figure 7-3 shows how the circuit behaves during thermal protection. During normal operation, the device acts as a buffer so the output is 3 V. When self heating causes the device junction temperature to increase above 140°C, the thermal protection forces the output to a high-impedance state and the output is pulled to ground through resistor RL.
The TLV910x features a resistive output stage capable of driving moderate capacitive loads, and by leveraging an isolation resistor, the device can easily be configured to drive large capacitive loads. Increasing the gain enhances the ability of the amplifier to drive greater capacitive loads; see Figure 7-4 and Figure 7-5. The particular op amp circuit configuration, layout, gain, and output loading are some of the factors to consider when establishing whether an amplifier will be stable in operation.
For additional drive capability in unity-gain configurations, improve capacitive load drive by inserting a small (10 Ω to 20 Ω) resistor, RISO, in series with the output, as shown in Figure 7-6. This resistor significantly reduces ringing and maintains DC performance for purely capacitive loads. However, if a resistive load is in parallel with the capacitive load, then a voltage divider is created, thus introducing a gain error at the output and slightly reducing the output swing. The error introduced is proportional to the ratio RISO / RL, and is generally negligible at low output levels. A high capacitive load drive makes the TLV910x well suited for applications such as reference buffers, MOSFET gate drives, and cable-shield drives. The circuit shown in Figure 7-6 uses an isolation resistor, RISO, to stabilize the output of an op amp. RISO modifies the open-loop gain of the system for increased phase margin.
The TLV910x is a 16-V, true rail-to-rail input operational amplifier with an input common-mode range that extends 100 mV beyond either supply rail. This wide range is achieved with paralleled complementary N-channel and P-channel differential input pairs, as shown in Figure 7-7. The N-channel pair is active for input voltages close to the positive rail, typically (V+) – 1 V to 100 mV above the positive supply. The P-channel pair is active for inputs from 100 mV below the negative supply to approximately (V+) – 2 V. There is a small transition region, typically (V+) –2 V to (V+) – 1 V in which both input pairs are on. This transition region can vary modestly with process variation, and within this region PSRR, CMRR, offset voltage, offset drift, noise, and THD performance can be degraded compared to operation outside this region. To achieve best performance with the TLV910x family, avoid this transition region when possible.
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress (EOS). These questions tend to focus on the device inputs, but can involve the supply voltage pins or even the output pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin. Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from accidental ESD events both before and during product assembly.
Having a good understanding of this basic ESD circuitry and its relevance to an electrical overstress event is helpful. Figure 7-8 shows an illustration of the ESD circuits contained in the TLV910x (indicated by the dashed line area). The ESD protection circuitry involves several current-steering diodes connected from the input and output pins and routed back to the internal power-supply lines, where the diodes meet at an absorption device or the power-supply ESD cell, internal to the operational amplifier. This protection circuitry is intended to remain inactive during normal circuit operation.
An ESD event is very short in duration and very high voltage (for example, 1 kV, 100 ns), whereas an EOS event is long duration and lower voltage (for example, 50 V, 100 ms). The ESD diodes are designed for out-of-circuit ESD protection (that is, during assembly, test, and storage of the device before being soldered to the PCB). During an ESD event, the ESD signal is passed through the ESD steering diodes to an absorption circuit (labeled ESD power-supply circuit). The ESD absorption circuit clamps the supplies to a safe level.
Although this behavior is necessary for out-of-circuit protection, excessive current and damage is caused if activated in-circuit. A transient voltage suppressors (TVS) can be used to prevent damage caused by turning on the ESD absorption circuit during an in-circuit ESD event. Using the appropriate current limiting resistors and TVS diodes allows for the use of device ESD diodes to protect against EOS events.
Overload recovery is defined as the time required for the op amp output to recover from a saturated state to a linear state. The output devices of the op amp enter a saturation region when the output voltage exceeds the rated operating voltage, either due to the high input voltage or the high gain. After the device enters the saturation region, the charge carriers in the output devices require time to return back to the linear state. After the charge carriers return back to the linear state, the device begins to slew at the specified slew rate. Thus, the propagation delay in case of an overload condition is the sum of the overload recovery time and the slew time. The overload recovery time for the TLV910x is approximately 1 µs.
Designers often have questions about a typical specification of an amplifier in order to design a more robust circuit. Due to natural variation in process technology and manufacturing procedures, every specification of an amplifier will exhibit some amount of deviation from the ideal value, like the input offset voltage of an amplifier. These deviations often follow Gaussian ("bell curve"), or normal distributions, and circuit designers can leverage this information to guardband their system, even when there is not a minimum or maximum specification in Section 6.7.
Figure 7-9 shows an example distribution, where µ, or mu, is the mean of the distribution, and where σ, or sigma, is the standard deviation of a system. For a specification that exhibits this kind of distribution, approximately two-thirds (68.26%) of all units can be expected to have a value within one standard deviation, or one sigma, of the mean (from µ–σ to µ+σ).
Depending on the specification, values listed in the typical column of Section 6.7 are represented in different ways. As a general rule of thumb, if a specification naturally has a nonzero mean (for example, gain bandwidth), then the typical value is equal to the mean (µ). However, if a specification naturally has a mean near zero (like input offset voltage), then the typical value is equal to the mean plus one standard deviation (µ + σ) in order to most accurately represent the typical value.
You can use this chart to calculate approximate probability of a specification in a unit; for example, for TLV910x, the typical input voltage offset is 300 µV, so 68.2% of all TLV910x devices are expected to have an offset from –300 µV to +300 µV. At 4 σ (±1200 µV), 99.9937% of the distribution has an offset voltage less than ±1200 µV, which means 0.0063% of the population is outside of these limits, which corresponds to about 1 in 15,873 units.
Specifications with a value in the minimum or maximum column are assured by TI, and units outside these limits will be removed from production material. For example, the TLV910x family has a maximum offset voltage of 1.5 mV at 25°C, and even though this corresponds to 5 σ (≈1 in 1.7 million units), which is extremely unlikely, TI assures that any unit with larger offset than 1.5 mV will be removed from production material.
For specifications with no value in the minimum or maximum column, consider selecting a sigma value of sufficient guardband for your application, and design worst-case conditions using this value. For example, the 6-σ value corresponds to about 1 in 500 million units, which is an extremely unlikely chance and can be an option as a wide guardband to design a system around. In this case, the TLV910x family does not have a maximum or minimum for offset voltage drift, but based on Figure 6-2 and the typical value of 0.6 µV/°C in Section 6.7, it can be calculated that the 6-σ value for offset voltage drift is about 3.6 µV/°C. When designing for worst-case system conditions, this value can be used to estimate the worst possible offset across temperature without having an actual minimum or maximum value.
However, process variation and adjustments over time can shift typical means and standard deviations, and unless there is a value in the minimum or maximum specification column, TI cannot assure the performance of a device. This information should be used only to estimate the performance of a device.
The TLV910x family is available in packages such as the WSON-8 (DSG) and WQFN-16 (RTE), which feature an exposed thermal pad. Inside the package, the die is attached to this thermal pad using an electrically conductive compound. For this reason, when using a package with an exposed thermal pad, the thermal pad must either be connected to V– or left floating. Attaching the thermal pad to a potential other than V– is not allowed, and performance of the device is not assured when doing so.
The TLV910xS devices feature one or more shutdown pins (SHDN) that disable the op amp, placing it into a low-power standby mode. In this mode, the op amp typically consumes about 20 µA. The SHDN pins are active high, meaning that shutdown mode is enabled when the input to the SHDN pin is a valid logic high. The amplifier is enabled when the input to the SHDN pin is a valid logic low.
The SHDN pins are referenced to the negative supply rail of the op amp. The threshold of the shutdown feature lies around 800 mV (typical) and does not change with respect to the supply voltage. Hysteresis has been included in the switching threshold to ensure smooth switching characteristics. To ensure optimal shutdown behavior, the SHDN pins should be driven with valid logic signals. A valid logic low is defined as a voltage between V– and V– + 0.2 V. A valid logic high is defined as a voltage between V– + 1.1 V and V+. The shutdown pin circuitry includes a pulldown resistor, which will inherently pull the voltage of the pin to the negative supply rail if not driven. Thus, to enable the amplifier, the SHDN pins should either be left floating or driven to a valid logic low. To disable the amplifier, the SHDN pins must be driven to a valid logic high. The maximum voltage allowed at the SHDN pins is V+ or V– + 20 V, whichever is lower. Exceeding this voltage level will damage the device.
The SHDN pins are high-impedance CMOS inputs. Channels of single and dual op amp packages are independently controlled, and channels of quad op amp packages are controlled in pairs. For battery-operated applications, this feature can be used to greatly reduce the average current and extend battery life. The typical enable time out of shutdown is 11 µs; disable time is 2.5 µs. When disabled, the output assumes a high-impedance state. This architecture allows the TLV910xS family to operate as a gated amplifier, multiplexer, or programmable-gain amplifier. Shutdown time (tOFF) depends on loading conditions and increases as load resistance increases. To ensure shutdown (disable) within a specific shutdown time, the specified 10-kΩ load to midsupply (VS / 2) is required. If using the TLV910xS without a load, the resulting turnoff time significantly increases.
The TLV910x has a single functional mode and is operational when the power-supply voltage is greater than 2.7 V (±1.35 V). The maximum power supply voltage for the TLV910x is 16 V (±8 V).
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.
The TLV910x family offers excellent DC precision and DC performance. These devices operate up to 16-V supply rails and offer true rail-to-rail input/output, low offset voltage and offset voltage drift, as well as 1.1-MHz bandwidth and high output drive. These features make the TLV910x a robust, high-performance operational amplifier for high-voltage industrial applications.
Many different systems require controlled voltages across numerous system nodes to ensure robust operation. A comparator can be used to monitor and control voltages by comparing a reference threshold voltage with an input voltage and providing an output when the input crosses this threshold.
The TLV910x family of op amps make excellent high voltage, precision comparators due to their robust input stage, low typical offset, and high slew rate. Previous generation high-voltage op amps often use back-to-back diodes across the inputs to prevent damage to the op amp which greatly limits these op amps to be used as comparators, but the patented input stage of the TLV910x allows the device to have a wide differential voltage between the inputs.
The primary objective is to design a 15-V precision comparator.
This noninverting comparator circuit applies the input voltage (VIN) to the noninverting terminal of the op amp. Two resistors (R1 and R2) divide the supply voltage (V+) to create a mid-supply threshold voltage (VTH) as calculated in Equation 1. The circuit is shown in Figure 8-1. When VIN is less then VTH, the output voltage transitions to the negative supply and equals the low-level output voltage. When VIN is greater than VTH, the output voltage transitions to the positive supply and equals the high-level output voltage.
In this example, resistor 1 and 2 have been selected to be 100 kΩ, which sets the reference threshold at 7.5 V. However, resistor 1 and 2 can be adjusted to modify the threshold using Equation 1. The values of resistor 1 and 2 have also been selected to reduce power consumption, but these values can be further increased to reduce power consumption, or reduced to improve noise performance.
The TLV910x is specified for operation from 2.7 V to 16 V (±1.35 V to ±8 V); many specifications apply from –40°C to 125°C.
Supply voltages larger than 20 V can permanently damage the device; see Section 6.1.
Place 0.1-µF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or high-impedance power supplies. For more detailed information on bypass capacitor placement, refer to Section 10.
For best operational performance of the device, use good PCB layout practices, including:
TINA™ is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI is a free, fully-functional version of the TINA software, preloaded with a library of macro models in addition to a range of both passive and active models. TINA-TI provides all the conventional DC, transient, and frequency domain analysis of SPICE, as well as additional design capabilities.
Available as a free download from the Analog eLab Design Center, TINA-TI offers extensive post-processing capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool.
These files require that either the TINA software (from DesignSoft™) or TINA-TI software be installed. Download the free TINA-TI software from the TINA-TI folder.
Texas Instruments, EMI Rejection Ratio of Operational Amplifiers application report
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. |
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. |
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