The TLV910x family (TLV9101, TLV9102, and TLV9104) is a family of 16-V general purpose operational amplifiers. This family offers excellent DC precision and AC performance, including rail-to-rail input/output, low offset (±300 µV, typ), low offset drift (±0.6 µV/°C, typ), and 1.1-MHz bandwidth.
Wide differential and common-mode input-voltage range, high output current (±80 mA, typ), high slew rate (4.5 V/µs, typ), low power operation (115 µA, typ) and shutdown functionality make the TLV910x a robust, low-power, high-performance operational amplifier for industrial applications.
The TLV910x family of op amps is available in micro-size packages, as well as standard packages, and is specified from –40°C to 125°C.
PART NUMBER (1) | PACKAGE | BODY SIZE (NOM) |
---|---|---|
TLV9101 | SOT-23 (5) | 2.90 mm × 1.60 mm |
SOT-23 (6) | 2.90 mm × 1.60 mm | |
SC70 (5) | 2.00 mm × 1.25 mm | |
SOT-553 (5)(2) | 1.60 mm × 1.20 mm | |
TLV9102 | SOIC (8) | 4.90 mm × 3.90 mm |
SOT-23 (8) | 2.90 mm × 1.60 mm | |
TSSOP (8) | 3.00 mm × 4.40 mm | |
VSSOP (8) | 3.00 mm × 3.00 mm | |
VSSOP (10) | 3.00 mm × 3.00 mm | |
WSON (8) | 2.00 mm × 2.00 mm | |
X2QFN (10) | 1.50 mm × 1.50 mm | |
TLV9104 | SOIC (14) | 8.65 mm × 3.90 mm |
TSSOP (14) | 5.00 mm × 4.40 mm | |
WQFN (16) | 3.00 mm × 3.00 mm | |
X2QFN (14) | 2.00 mm × 2.00 mm |
Changes from Revision D (June 2021) to Revision E (August 2021)
Changes from Revision C (May 2020) to Revision D (June 2021)
Changes from Revision B (May 2020) to Revision C (May 2020)
Changes from Revision A (April 2019) to Revision B (May 2020)
PIN | I/O | DESCRIPTION | ||
---|---|---|---|---|
NAME | DBV | DCK and DRL | ||
+IN | 3 | 1 | I | Noninverting input |
–IN | 4 | 3 | I | Inverting input |
OUT | 1 | 4 | O | Output |
V+ | 5 | 5 | — | Positive (highest) power supply |
V– | 2 | 2 | — | Negative (lowest) power supply |
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
IN+ | 3 | I | Noninverting input |
IN– | 4 | I | Inverting input |
OUT | 1 | O | Output |
SHDN | 5 | I | Shutdown: low = amplifier enabled, high = amplifier disabled. See Section 7.3.10 for more information. |
V+ | 6 | — | Positive (highest) power supply |
V– | 2 | — | Negative (lowest) power supply |
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
IN1+ | 3 | I | Noninverting input, channel 1 |
IN1– | 2 | I | Inverting input, channel 1 |
IN2+ | 5 | I | Noninverting input, channel 2 |
IN2– | 6 | I | Inverting input, channel 2 |
OUT1 | 1 | O | Output, channel 1 |
OUT2 | 7 | O | Output, channel 2 |
V+ | 8 | — | Positive (highest) power supply |
V– | 4 | — | Negative (lowest) power supply |
PIN | I/O | DESCRIPTION | ||
---|---|---|---|---|
NAME | VSSOP | X2QFN | ||
IN1+ | 3 | 10 | I | Noninverting input, channel 1 |
IN1– | 2 | 9 | I | Inverting input, channel 1 |
IN2+ | 7 | 4 | I | Noninverting input, channel 2 |
IN2– | 8 | 5 | I | Inverting input, channel 2 |
OUT1 | 1 | 8 | O | Output, channel 1 |
OUT2 | 9 | 6 | O | Output, channel 2 |
SHDN1 | 5 | 2 | I | Shutdown, channel 1: low = amplifier enabled, high = amplifier disabled. See Section 7.3.10 for more information. |
SHDN2 | 6 | 3 | I | Shutdown, channel 2: low = amplifier enabled, high = amplifier disabled. See Section 7.3.10 for more information. |
V+ | 10 | 7 | — | Positive (highest) power supply |
V– | 4 | 1 | — | Negative (lowest) power supply |
PIN | I/O | DESCRIPTION | |||
---|---|---|---|---|---|
NAME | SOIC and TSSOP | WQFN | X2QFN | ||
IN1+ | 3 | 1 | 2 | I | Noninverting input, channel 1 |
IN1– | 2 | 16 | 1 | I | Inverting input, channel 1 |
IN2+ | 5 | 3 | 4 | I | Noninverting input, channel 2 |
IN2– | 6 | 4 | 5 | I | Inverting input, channel 2 |
IN3+ | 10 | 10 | 9 | I | Noninverting input, channel 3 |
IN3– | 9 | 9 | 8 | I | Inverting input, channel 3 |
IN4+ | 12 | 12 | 11 | I | Noninverting input, channel 4 |
IN4– | 13 | 13 | 12 | I | Inverting input, channel 4 |
NC | — | 6, 7 | — | — | Do not connect |
OUT1 | 1 | 15 | 14 | O | Output, channel 1 |
OUT2 | 7 | 5 | 6 | O | Output, channel 2 |
OUT3 | 8 | 8 | 7 | O | Output, channel 3 |
OUT4 | 14 | 14 | 13 | O | Output, channel 4 |
V+ | 4 | 2 | 3 | — | Positive (highest) power supply |
V– | 11 | 11 | 10 | — | Negative (lowest) power supply |
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
IN1+ | 1 | I | Noninverting input, channel 1 |
IN1– | 16 | I | Inverting input, channel 1 |
IN2+ | 3 | I | Noninverting input, channel 2 |
IN2– | 4 | I | Inverting input, channel 2 |
IN3+ | 10 | I | Noninverting input, channel 3 |
IN3– | 9 | I | Inverting input, channel 3 |
IN4+ | 12 | I | Noninverting input, channel 4 |
IN4– | 13 | I | Inverting input, channel 4 |
OUT1 | 15 | O | Output, channel 1 |
OUT2 | 5 | O | Output, channel 2 |
OUT3 | 8 | O | Output, channel 3 |
OUT4 | 14 | O | Output, channel 4 |
SHDN12 | 6 | I | Shutdown, channels 1 and 2: low = amplifiers enabled, high = amplifiers disabled. See Section 7.3.10 for more information. |
SHDN34 | 7 | I | Shutdown, channels 3 and 4: low = amplifiers enabled, high = amplifiers disabled. See Section 7.3.10 for more information. |
V+ | 2 | — | Positive (highest) power supply |
V– | 11 | — | Negative (lowest) power supply |