SBOS943E February   2019  – August 2021 TLV9101 , TLV9102 , TLV9104

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information for Single Channel
    5. 6.5 Thermal Information for Dual Channel
    6. 6.6 Thermal Information for Quad Channel
    7. 6.7 Electrical Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  EMI Rejection
      2. 7.3.2  Phase Reversal Protection
      3. 7.3.3  Thermal Protection
      4. 7.3.4  Capacitive Load and Stability
      5. 7.3.5  Common-Mode Voltage Range
      6. 7.3.6  Electrical Overstress
      7. 7.3.7  Overload Recovery
      8. 7.3.8  Typical Specifications and Distributions
      9. 7.3.9  Packages With an Exposed Thermal Pad
      10. 7.3.10 Shutdown
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 High Voltage Precision Comparator
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 TINA-TI (Free Software Download)
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Thermal Information for Dual Channel

THERMAL METRIC(1) TLV9102, TLV9102S UNIT
D
(SOIC)		 DDF
(SOT-23-8)		 DGK
(VSSOP)		 DGS
(VSSOP)		 DSG
(WSON)		 PW
(TSSOP)		 RUG
(X2QFN)
8 PINS 8 PINS 8 PINS 10 PINS 8 PINS 8 PINS 10 PINS
RθJA Junction-to-ambient thermal resistance 138.7 150.4 189.3 152.2 81.6 188.4 149.6 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 78.7 85.6 75.8 67.3 101.6 77.1 58.3 °C/W
RθJB Junction-to-board thermal resistance 82.2
70.0

 111.0 95.5 48.3 119.1 77.7 °C/W
ψJT Junction-to-top characterization parameter 27.8 8.1 15.4 67.9 6.0 14.2 1.3 °C/W
ψJB Junction-to-board characterization parameter 81.4 69.6 109.3 94.3 48.3 117.4 77.5 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A N/A N/A 22.8 N/A N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.