SBOSA68D November   2021  – March 2024 TLV9161 , TLV9162 , TLV9164

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information for Single Channel
    5. 5.5 Thermal Information for Dual Channel
    6. 5.6 Thermal Information for Quad Channel
    7. 5.7 Electrical Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Input Protection Circuitry
      2. 6.3.2  EMI Rejection
      3. 6.3.3  Thermal Protection
      4. 6.3.4  Capacitive Load and Stability
      5. 6.3.5  Common-Mode Voltage Range
      6. 6.3.6  Phase Reversal Protection
      7. 6.3.7  Electrical Overstress
      8. 6.3.8  Overload Recovery
      9. 6.3.9  Typical Specifications and Distributions
      10. 6.3.10 Packages With an Exposed Thermal Pad
      11. 6.3.11 Shutdown
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Low-Side Current Measurement
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curve
      2. 7.2.2 Buffered Multiplexer
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 TINA-TI (Free Software Download)
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3.4 Capacitive Load and Stability

The TLV916x features an output stage capable of driving moderate capacitive loads, and by leveraging an isolation resistor, the device can easily be configured to drive larger capacitive loads. Increasing the gain enhances the ability of the amplifier to drive greater capacitive loads; see Figure 6-5 and Figure 6-6. The particular op amp circuit configuration, layout, gain, and output loading are some of the factors to consider when establishing whether an amplifier will be stable in operation.

GUID-20211103-SS0I-R07T-DNQR-PDWFWDSJ9TTZ-low.gifFigure 6-5 Small-Signal Overshoot vs Capacitive Load (20-mVpp Output Step, G = +1)
GUID-20211103-SS0I-DX6H-MQNZ-PTBCBXDNSGFX-low.gifFigure 6-6 Small-Signal Overshoot vs Capacitive Load (20-mVpp Output Step, G = -1)

For additional drive capability in unity-gain configurations, improve capacitive load drive by inserting a small resistor, RISO, in series with the output, as shown in Figure 6-7. This resistor significantly reduces ringing and maintains DC performance for purely capacitive loads. However, if a resistive load is in parallel with the capacitive load, then a voltage divider is created, thus introducing a gain error at the output and slightly reducing the output swing. The error introduced is proportional to the ratio RISO / RL, and is generally negligible at low output levels. A high capacitive load drive makes the TLV916x well suited for applications such as reference buffers, MOSFET gate drives, and cable-shield drives. The circuit shown in Figure 6-7 uses an isolation resistor, RISO, to stabilize the output of an op amp. RISO modifies the open-loop gain of the system for increased phase margin.

GUID-EE46E065-5E94-4E51-88A4-A114BA5AE7AD-low.gifFigure 6-7 Extending Capacitive Load Drive With the TLV9161