SBOSAD7A April   2023  – August 2024 TLV9161-Q1 , TLV9162-Q1 , TLV9164-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information for Single Channel
    5. 5.5 Thermal Information for Dual Channel
    6. 5.6 Thermal Information for Quad Channel
    7. 5.7 Electrical Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Input Protection Circuitry
      2. 6.3.2 EMI Rejection
      3. 6.3.3 Thermal Protection
      4. 6.3.4 Capacitive Load and Stability
      5. 6.3.5 Common-Mode Voltage Range
      6. 6.3.6 Phase Reversal Protection
      7. 6.3.7 Electrical Overstress
      8. 6.3.8 Overload Recovery
      9. 6.3.9 Typical Specifications and Distributions
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Low-Side Current Measurement
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 TINA-TI (Free Software Download)
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.3.5 Common-Mode Voltage Range

The TLV916x-Q1 is a 16V, rail-to-rail input operational amplifier with an input common-mode range that extends to both supply rails. This wide range is achieved with paralleled complementary N-channel and P-channel differential input pairs, as shown in Figure 6-8. The N-channel pair is active for input voltages close to the positive rail, typically from (V+) – 1V to the positive supply. The P-channel pair is active for inputs from the negative supply to approximately (V+) – 2V. There is a small transition region, typically (V+) – 2V to (V+) – 1V in which both input pairs are on. This transition region can vary modestly with process variation. Within this region PSRR, CMRR, offset voltage, offset drift, noise, and THD performance may be degraded compared to operation outside this region.

Figure 5-5 shows this transition region for a typical device in terms of input voltage offset in more detail.

For more information on common-mode voltage range and PMOS/NMOS pair interaction, see Op Amps With Complementary-Pair Input Stages application note.

TLV9161-Q1 TLV9162-Q1 TLV9164-Q1 Rail-to-Rail Input StageFigure 6-8 Rail-to-Rail Input Stage