SBOSAD7A April   2023  – August 2024 TLV9161-Q1 , TLV9162-Q1 , TLV9164-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information for Single Channel
    5. 5.5 Thermal Information for Dual Channel
    6. 5.6 Thermal Information for Quad Channel
    7. 5.7 Electrical Characteristics
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Input Protection Circuitry
      2. 6.3.2 EMI Rejection
      3. 6.3.3 Thermal Protection
      4. 6.3.4 Capacitive Load and Stability
      5. 6.3.5 Common-Mode Voltage Range
      6. 6.3.6 Phase Reversal Protection
      7. 6.3.7 Electrical Overstress
      8. 6.3.8 Overload Recovery
      9. 6.3.9 Typical Specifications and Distributions
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Low-Side Current Measurement
        1. 7.2.1.1 Design Requirements
        2. 7.2.1.2 Detailed Design Procedure
        3. 7.2.1.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Development Support
        1. 8.1.1.1 TINA-TI (Free Software Download)
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Pin Configuration and Functions

TLV9161-Q1 TLV9162-Q1 TLV9164-Q1 TLV9161-Q1 DBV Package,5-Pin SOT-23(Top View)Figure 4-1 TLV9161-Q1 DBV Package,
5-Pin SOT-23
(Top View)
TLV9161-Q1 TLV9162-Q1 TLV9164-Q1 TLV9161-Q1 DCK Package,5-Pin SC70(Top View)Figure 4-2 TLV9161-Q1 DCK Package,
5-Pin SC70
(Top View)
Table 4-1 Pin Functions: TLV9161-Q1
PINTYPE(1)DESCRIPTION
NAMESOT-23 (DBV)SC70 (DCK)
IN+31INoninverting input
IN–43IInverting input
OUT14OOutput
V+55—Positive (highest) power supply
V–22—Negative (lowest) power supply
(1) I = input, O = output
TLV9161-Q1 TLV9162-Q1 TLV9164-Q1 TLV9162-Q1 D, PW, and DGK Package,8-Pin SOIC, TSSOP, and VSSOP(Top View)Figure 4-3 TLV9162-Q1 D, PW, and DGK Package,
8-Pin SOIC, TSSOP, and VSSOP
(Top View)
Table 4-2 Pin Functions: TLV9162-Q1
PINTYPE(1)DESCRIPTION
NAMENO.
IN1+3INoninverting input, channel 1
IN1–2IInverting input, channel 1
IN2+5INoninverting input, channel 2
IN2–6IInverting input, channel 2
OUT11OOutput, channel 1
OUT27OOutput, channel 2
V+8—Positive (highest) power supply
V–4—Negative (lowest) power supply
(1) I = input, O = output
TLV9161-Q1 TLV9162-Q1 TLV9164-Q1 TLV9164-Q1 D and PW Package,14-Pin SOIC and TSSOP(Top View)Figure 4-4 TLV9164-Q1 D and PW Package,
14-Pin SOIC and TSSOP
(Top View)
Table 4-3 Pin Functions: TLV9164-Q1
PINTYPE(1)DESCRIPTION
NAMENO.
IN1+3INoninverting input, channel 1
IN1–2IInverting input, channel 1
IN2+5INoninverting input, channel 2
IN2–6IInverting input, channel 2
IN3+10INoninverting input, channel 3
IN3–9IInverting input, channel 3
IN4+12INoninverting input, channel 4
IN4–13IInverting input, channel 4
OUT11OOutput, channel 1
OUT27OOutput, channel 2
OUT38OOutput, channel 3
OUT414OOutput, channel 4
V+4—Positive (highest) power supply
V–11—Negative (lowest) power supply
(1) I = input, O = output