SBOSA67B November   2021  – March 2022 TLV9361 , TLV9362 , TLV9364

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information for Single Channel
    5. 6.5 Thermal Information for Dual Channel
    6. 6.6 Thermal Information for Quad Channel
    7. 6.7 Electrical Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 EMI Rejection
      2. 7.3.2 Thermal Protection
      3. 7.3.3 Capacitive Load and Stability
      4. 7.3.4 Electrical Overstress
      5. 7.3.5 Overload Recovery
      6. 7.3.6 Typical Specifications and Distributions
    4. 7.4 Device Functional Modes
  8. 8 Application Information Disclaimer
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Unity-Gain Buffer With RISO Stability Compensation
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
        1. 11.1.1.1 TINA-TI (Free Software Download)
        2. 11.1.1.2 TI Precision Designs
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.1.2 Detailed Design Procedure

Figure 8-1 shows a unity-gain buffer driving a capacitive load. Equation 1 shows the transfer function for the circuit in Figure 8-1. Figure 8-1 does not show the open-loop output resistance of the operational amplifier (Ro).

Equation 1. GUID-47E65001-FC75-40CF-A03B-27B5FBD9A7A8-low.gif

The transfer function in Equation 1 has a pole and a zero. The frequency of the pole (fp) is determined by (Ro + RISO) and CLOAD. The RISO and CLOAD components determine the frequency of the zero (fz). A stable system is obtained by selecting RISO so that the rate of closure (ROC) between the open-loop gain (AOL) and 1/β is 20 dB per decade. Figure 8-2 shows the concept. The 1/β curve for a unity-gain buffer is 0 dB.

GUID-6ED62CAA-7785-469B-BDBD-706C6A58803D-low.gifFigure 8-2 Unity-Gain Amplifier With RISO Compensation

Typically, ROC stability analysis is simulated. The validity of the analysis depends on multiple factors, especially the accurate modeling of Ro. In addition to simulating the ROC, a robust stability analysis includes a measurement of overshoot percentage and/or AC gain peaking of the circuit using a function generator, oscilloscope, and gain and phase analyzer. Phase margin is then calculated from these measurements. Table 8-1 shows the overshoot percentage and AC gain peaking that correspond to a phase margin of 45°. For more details on this design and other alternative devices that can replace the TLV936x, see the Capacitive Load Drive Solution Using an Isolation Resistor precision design.

Table 8-1 Phase Margin versus Overshoot and AC Gain Peaking
PHASE MARGINOVERSHOOTAC GAIN PEAKING
45°23.3%2.35 dB