SLVSH63 February   2023 TLVM13610

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 System Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Input Voltage Range (VIN1, VIN2)
      2. 8.3.2  Adjustable Output Voltage (FB)
      3. 8.3.3  Input Capacitors
      4. 8.3.4  Output Capacitors
      5. 8.3.5  Switching Frequency (RT)
      6. 8.3.6  Precision Enable and Input Voltage UVLO (EN)
      7. 8.3.7  Power-Good Monitor (PG)
      8. 8.3.8  Adjustable Switch-Node Slew Rate (RBOOT, CBOOT)
      9. 8.3.9  Bias Supply Regulator (VCC, VLDOIN)
      10. 8.3.10 Overcurrent Protection (OCP)
      11. 8.3.11 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
      2. 8.4.2 Standby Mode
      3. 8.4.3 Active Mode
  9. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Design 1 – High-Efficiency 8-A (10-A peak) Synchronous Buck Regulator for Industrial Applications
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Custom Design with WEBENCH® Tools
          2. 9.2.1.2.2 Output Voltage Setpoint
          3. 9.2.1.2.3 Switching Frequency Selection
          4. 9.2.1.2.4 Input Capacitor Selection
          5. 9.2.1.2.5 Output Capacitor Selection
          6. 9.2.1.2.6 Other Connections
        3. 9.2.1.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Thermal Design and Layout
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
      2. 10.1.2 Development Support
        1. 10.1.2.1 Custom Design with WEBENCH® Tools
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.2.1.1 Design Requirements

#GUID-2059F019-A291-47D3-A225-BCC8D8842653/SNVSB296210 shows the intended input, output, and performance parameters for this application example. Note that if the input voltage decreases below approximately 6 V, the regulator operates in dropout with the output voltage below its 5-V setpoint.

Table 9-1 Design Parameters
DESIGN PARAMETERVALUE
Input voltage range9 V to 36 V
Input voltage UVLO turn on, off6 V, 4.3 V
Output voltage5 V
Maximum output current8 A
Switching frequency1 MHz
Output voltage regulation±1%
Module shutdown current< 1 µA

#GUID-2059F019-A291-47D3-A225-BCC8D8842653/SNVSB29632 gives the selected buck module power-stage components with availability from multiple vendors. This design uses an all-ceramic output capacitor implementation.

Table 9-2 List of Materials for Application Circuit 1
REFERENCE DESIGNATORQTYSPECIFICATIONMANUFACTURER(1)PART NUMBER
CIN1, CIN2210 µF, 50 V, X7R, 1210, ceramicTaiyo YudenUMJ325KB7106KMHT
TDKCNA6P1X7R1H106K
10 µF, 50 V, X7S, 1210, ceramicMurataGCM32EC71H106KA03
TDKCGA6P3X7S1H106M
COUT1, COUT2,COUT3347 µF, 6.3 V, X7R, 1210, ceramicMurataGRM32ER70J476ME20K
AVX12106C476MAT2A
47 µF, 10 V, X7R, 1210, ceramicMurataGRM32ER71A476ME15L
AVX1210ZC476MAT2A
100 µF, 6.3 V, X7S, 1210, ceramicMurataGRM32EC70J107ME15L
U11TLVM13610 36-V, 8-A synchronous buck moduleTexas InstrumentsTLVM13610RDLR

More generally, the TLVM13610 module is designed to operate with a wide range of external components and system parameters. However, the integrated loop compensation is optimized for a certain range of output capacitance.