SLVSH63 February   2023 TLVM13610

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 System Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Input Voltage Range (VIN1, VIN2)
      2. 8.3.2  Adjustable Output Voltage (FB)
      3. 8.3.3  Input Capacitors
      4. 8.3.4  Output Capacitors
      5. 8.3.5  Switching Frequency (RT)
      6. 8.3.6  Precision Enable and Input Voltage UVLO (EN)
      7. 8.3.7  Power-Good Monitor (PG)
      8. 8.3.8  Adjustable Switch-Node Slew Rate (RBOOT, CBOOT)
      9. 8.3.9  Bias Supply Regulator (VCC, VLDOIN)
      10. 8.3.10 Overcurrent Protection (OCP)
      11. 8.3.11 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Shutdown Mode
      2. 8.4.2 Standby Mode
      3. 8.4.3 Active Mode
  9. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Design 1 – High-Efficiency 8-A (10-A peak) Synchronous Buck Regulator for Industrial Applications
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Custom Design with WEBENCH® Tools
          2. 9.2.1.2.2 Output Voltage Setpoint
          3. 9.2.1.2.3 Switching Frequency Selection
          4. 9.2.1.2.4 Input Capacitor Selection
          5. 9.2.1.2.5 Output Capacitor Selection
          6. 9.2.1.2.6 Other Connections
        3. 9.2.1.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Thermal Design and Layout
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
      2. 10.1.2 Development Support
        1. 10.1.2.1 Custom Design with WEBENCH® Tools
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  11. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.4.1 Layout Guidelines

The following list summarizes the essential guidelines for PCB layout and component placement to optimze DC/DC module performance, including thermals and EMI signature. GUID-F713B0B5-529D-44FC-A9F6-8EDEE257E469.html#SLVSA437079 and GUID-F713B0B5-529D-44FC-A9F6-8EDEE257E469.html#SLVSAW7_LAYER2 show a recommended PCB layout for the TLVM13610 with optimized placement and routing of the power-stage and small-signal components.

  • Place input capacitors as close as possible to the VIN pins. Note the dual and symmetrical arrangement of the input capacitors based on the VIN1 and VIN2 pins located on each side of the module package. The high-frequency currents are split in two and effectively flow in opposing directions such that the related magnetic fields contributions cancel each other, leading to improved EMI performance.
    • Use low-ESR 1206 or 1210 ceramic capacitors with X7R or X7S dielectric. The module has integrated dual 0402 input capacitors for high-frequency bypass.
    • Ground return paths for the input capacitors must consist of localized top-side planes that connect to the PGND pads under the module.
    • Even though the VIN pins are connected internally, use a wide polygon plane on a lower PCB layer to connect these pins together and to the input supply.
  • Place output capacitors as close as possible to the VOUT pins. A similar dual and symmetrical arrangement of the output capacitors enables magnetic field cancellation and EMI mitigation.
    • Ground return paths for the output capacitors must consist of localized top-side planes that connect to the PGND pads under the module.
    • Even though the VOUT pins are connected internally, use a wide polygon plane on a lower PCB layer to connect these pins together and to the load, thus reducing conduction loss and thermal stress.
  • Keep the FB trace as short as possible by placing the feedback resistors close to the FB pin. Reduce noise sensitivity of the output voltage feedback path by placing the resistor divider close to the FB pin, rather than close to the load. FB is the input to the voltage-loop error anplifier and represents a high-impedance node sensitive to noise. Route a trace from the upper feedback resistor to the required point of output voltage regulation.
  • Use a solid ground plane on the PCB layer directly below the top layer with the module. This plane acts as a noise shield by minimizing the magnetic fields associated with the currents in the switching loops. Connect AGND pins 6 and 11 directly to PGND pin 19 under the module.
  • Provide enough PCB area for proper heatsinking. Use sufficient copper area to acheive a low thermal impedance commensurate with the maximum load current and ambient temperature conditions. Provide adequate heatsinking for the TLVM13610 to keep the junction temperature below 150°C. For operation at full rated load, the top-side ground plane is an important heat-dissipating area. Use an array of heat-sinking vias to connect the exposed pads (PGND) of the package to the PCB ground plane. If the PCB has multiple copper layers, connect these thermal vias to inner-layer ground planes. Make the top and bottom PCB layers preferably with two-ounce copper thickness (and no less than one ounce).