SLVSFT6B May 2021 – January 2022 TLVM13630
PRODUCTION DATA
Place a 1-µF capacitor between the VCC pin and PGND, located near to the device.
The right-half-plane zero of an IBB topology is at its lowest frequency at minimum input voltage. However, it does not appear at low frequency for a –5 V output and thus has minimal effect on the loop response for this application.
In the inverting buck-boost configuration, the input capacitor CIN and output capacitor COUT can formed an AC capacitive divider during a fast VIN transient or hot-plugged event at the input. This event will resulted in a positive voltage spike at the output that may disturb the load. In this case, an optional Schottky diode may be installed between –VOUT and GND as shown in Figure 8-12 to clamp the output spike.