SLVSHP0 July   2024 TLVM14404 , TLVM14406

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 System Characteristics
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input Voltage Range (VIN1, VIN2)
      2. 7.3.2  Enable EN Pin and Use as VIN UVLO
      3. 7.3.3  CONFIG Device Configuration Pin
      4. 7.3.4  Adjustable Switching Frequency
      5. 7.3.5  Adjustable Output Voltage (FB)
      6. 7.3.6  Input Capacitors
      7. 7.3.7  Output Capacitors
      8. 7.3.8  Power-Good Output Voltage Monitoring
      9. 7.3.9  Bias Supply Regulator (VCC, VOSNS)
      10. 7.3.10 Overcurrent Protection (OCP)
      11. 7.3.11 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Standby Mode
      3. 7.4.3 Active Mode
  9. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Design 1 – High-efficiency, Dual Output 5V at 3A, 3.3V at 3A, Synchronous Buck Regulator
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Custom Design With WEBENCH® Tools
          2. 8.2.1.2.2 Output Voltage Setpoint
          3. 8.2.1.2.3 Switching Frequency Selection
          4. 8.2.1.2.4 Input Capacitor Selection
          5. 8.2.1.2.5 Output Capacitor Selection
          6. 8.2.1.2.6 Other Considerations
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Design 2 – High-efficiency, 6A, Synchronous Buck Regulator for Industrial Applications
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 Output Voltage Setpoint
          2. 8.2.2.2.2 Switching Frequency Selection
          3. 8.2.2.2.3 Input Capacitor Selection
          4. 8.2.2.2.4 Output Capacitor Selection
          5. 8.2.2.2.5 Other Connections
        3. 8.2.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Thermal Design and Layout
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
      2. 9.1.2 Development Support
        1. 9.1.2.1 Custom Design With WEBENCH® Tools
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

RCH package, 28-pin QFN-FCMOD with Wettable Flanks

TLVM14404 TLVM14406 Dual Output (Top View) Figure 5-1 Dual Output (Top View)
TLVM14404 TLVM14406 Single Output Primary (Top View) Figure 5-2 Single Output Primary (Top View)
Table 5-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NO. NAME
DUAL OUTPUT SINGLE OUTPUT
14 VIN2 VIN2 I Input supply to the regulator. Connect a high quality bypass capacitors from this pin to PGND. Low impedance connection must be provided to VIN1.
15 BOOT2 BOOT2 I/O Channel 2 high-side driver upper supply rail. Connected to an internal 100nF capacitor between SW2 and BOOT2. An internal diode charges the capacitor while SW2 is low. Mechanical connection, use as NC in design.
16, 17 SW2 SW2 P Channel 2 Switching node that is internally connected to the source of the high-side NMOS buck switch and the drain of the low-side NMOS synchronous rectifier. Mechanical connection, use as NC in design.
22, 23 SW1 SW1 P Channel 1 Switching node that is internally connected to the source of the high-side NMOS buck switch and the drain of the low-side NMOS synchronous rectifier. Mechanical connection, use as NC in design.
24 BOOT1 BOOT1 I/O Channel 1 High-side driver upper supply rail. Connected to an internal 100nF between SW1 and BOOT1. An internal diode charges the capacitor while SW1 is low. Mechanical connection, use as NC in design.
25 VIN1 VIN1 I Input supply to the regulator. Connect a high quality bypass capacitors from this pin to PGND. Low impedance connection must be provided to VIN2.
27 GND GND G Analog ground connection. Ground return for the internal logic.
1 PG1 PG1 O Dual function pin. An open drain output that transitions low if VOSNS1 is outside a specified regulation window in dual output and single output primary configuration.
2 EN1 EN1 I An active high input TLVM1440x (VOH > 1.375V) enables Output 1 in dual output operation. When in single output operation, an active high input enables all phases in the system. When disabled, the TLVM1440x is in shutdown mode. EN1 must never be floating.
3 BIAS & VOSNS1 BIAS & VOSNS1 I Output voltage sense and input to internal voltage regulator. Connect to non-switching side of the inductor. Connect an optional high quality 0.1μF capacitor from this pin to AGND for best performance.
4 FB1 FB1 I Feedback input to channel 1 of the TLVM1440x in dual output operation and feedback input to all channels in single output operation. Connect FB1 to VCC through a 10kΩ resistor for a 5V output or connect FB1 to AGND for a 3.3V output. A resistive divider from the non-switching side of the inductor to FB1 sets the output voltage level between 0.8V and 20V. The regulation threshold at FB1 is 0.8V. For lower output voltages use at least a 10kΩ for the top of the resistor divider.
5 VCC VCC O Internal regulator output. Used as supply to internal control circuits. Do not connect to any external loads. Connect a high quality 1μF capacitor from this pin to AGND.
6 AGND AGND G Analog ground connection. Ground return for the internal voltage reference and analog circuits.
7 RT RT I Frequency programming pin. A resistor from RT to AGND sets the oscillator frequency between 100kHz and 2.2MHz.
8 FB2 SS I Dual function pin. When in dual output operation, the pin functions as FB2, feedback input to channel 2 of the TLVM1440x. Connect FB2 to VCC through a 10kΩ resistor for a 5V output or connect FB2 to AGND for a 3.3V output. A resistive divider from the non-switching side of the inductor to FB2 sets the output voltage level between 0.8V and 20V. For lower output voltages use at least a 10kΩ for the top of the resistor divider. When in single output mode, the pin functions as SS. An external capacitor must be placed from SS to AGND for external soft start of the output. Connect the SS pins of primary and secondaries for fault communication between devices.
9 VOSNS2 COMP I Dual function pin. In dual output operation, the pin functions as VOSNS2 for the fixed 3.3V and 5V and adjustable output conditions. In single output operation, the pin is the output of the internal error amplifier.
10 EN2 EN2 I An active high input (VOH > 1.375V) enables Output 2 in dual output operation. When in single output mode, EN2 of all TLVM1440x must be connected together. An active high input enables all secondary phases in the system. When disabled, only one channel in the primary TLVM1440x is active while all remaining phases are in shutdown mode. EN2 must never be floating.
11 CONFIG CONFIG I Single or Dual output selection. Connect specific resistor values to the pin (refer to Table 7-1) to select number of phases, primary and secondary and dither options.
12 PG2 NC O Dual function pin. In dual output operation, this pin behaves as PG2, an open drain output that transitions low if VOSNS2 is outside a specified regulation window. In single output mode, leave the pin floating.
18, 19 VOUT2 VOUT O Output of module. Connect a high quality bypass capacitors from this pin to PGND.
20, 21 VOUT1 VOUT O Output of module. Connect a high quality bypass capacitors from this pin to PGND.
13. 26 PGND PGND G Power ground to internal low side MOSFET. Connect to system ground. Low impedance connection must be provided to PGND1, PGND3 and PGND4. Connect a high quality bypass capacitors from this pin to VIN2.
28 PGND PGND G Power ground and heat sink connection. Solder directly to system ground plane. Low impedance connection must be provided to other PGND pins.
(1) I = input, O = output, P = power, G = ground